Abstract: Casing installation assemblies for installing a casing within a borehole, as well as systems and methods related thereto are disclosed. In an embodiment, the casing installation assembly includes a tubular string, an isolation sub coupled to a downhole end of the tubular string, and a diverter sub coupled to and positioned downhole of the isolation sub. In addition, the casing installation assembly includes a landing string coupled to the diverter sub and configured to be coupled to the casing. The isolation sub includes a valve assembly that is configured to selectively prevent fluid communication between the tubular string and the diverter sub.

Abstract: A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.

Abstract: The system and method of retractable solar arrays for underwater vehicles. In some cases, the retractable solar arrays for underwater vehicles contain anti-biofouling mechanisms. The retractable solar arrays may extend in a linear or a fan-like manner. In some cases, the solar array may be wrapped around the outside of the underwater vehicle or within a cylindrical housing. In some cases the solar array is a single flexible member with a series of connected panels.

Abstract: In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration.

Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the at least six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy. The at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate. A first inverter formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in either the first deck or the second deck.

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes depositing a resin film on a substrate that has microfabricated structures defining recesses. The resin film fills the recesses and covers the microfabricated structures. The method includes performing, using a photoacid generator (PAG)-based process, a localized removal of the resin film to remove the resin film to respective first depths in the recesses, at least two depths of the respective first depths being different depths. The method includes repeatedly performing, using a thermal acid generator (TAG)-based process and until a predetermined condition is met, a uniform removal of a remaining portion of the resin film to remove a substantially uniform depth of the resin film in the recesses.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.

Abstract: A system and method for performing a financial transaction by determining a master account number associated with one or more accounts that a user may access, providing data to generate a user interface displaying a list of the accounts and an indicator associated with a financial transaction, receiving indicator information associating the indicator with one or more of the accounts, receiving terms for the financial transaction, and performing the financial transaction. The list of accounts may be expanded to view account information.

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.

Abstract: A semiconductor device includes a transistor stack. The transistor stack has a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors. The semiconductor device also includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack, and are electrically coupled to the transistor stack.

Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.

Abstract: Various embodiments of the present invention provide methods, apparatus, systems, computing devices, computing entities, and/or the like for performing predictive data analysis. Certain embodiments of the present invention utilize systems, methods, and computer program products that perform predictive data analysis by using at least one of prospective coverage score determination machine learning models and prospective event-based classification machine learning models.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.