Abstract: An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a first stack of transistors and a second stack of transistors. The first stack includes a first transistor and a second transistor stacked on the first transistor along a Z direction perpendicular to a substrate plane. The second stack includes a third transistor and a fourth transistor stacked on the third transistor along the Z direction. The semiconductor apparatus includes a first routing track and a second routing track electrically isolated from the first routing track. The first and second routing tracks extend in an X direction parallel to the substrate plane. A first and fourth conductive trace conductively couple a first gate of the first transistor and a fourth gate of the fourth transistor to the first routing track, respectively. A first terminal structure conductively couples four source/drain terminals of the first, second, third and fourth transistors, respectively.

Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.

Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: Provided herein are compounds and pharmaceutical compositions useful for treating meibomian gland dysfunction (MGD), comprising administering to a subject in need thereof a therapeutically effective amount of a compound of Formula (I) or a compound of Formula (I?), or pharmaceutical composition described herein.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

Abstract: A neuromodulation catheter is positionable in a blood vessel having a wall for use in delivering therapeutic energy to targets external to the blood vessel. An electrically insulative substrate such as an elongate finger is carried at a distal end of the catheter body. The substrate has a first face carrying a plurality of electrodes, and a second face on an opposite side of the substrate from the first face. The finger is biased such that when expanded within the blood vessel, it forms a spiral configuration with the first face facing outwardly to bias the electrodes in contact with the blood vessel wall.

Abstract: A urinal assembly having a frame and a plurality of posts or posts extending from the frame. The frame can include a plurality of openings. The openings can be defined by a plurality of sides and corners. The posts can extend from the corners and/or from the sides of the openings. In some embodiments, posts extend from a first face and a second face of the frame.

Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.

Abstract: Provided are compounds that enhance the efficacy of viruses by increasing spread of the virus in cells, increasing the titer of virus in cells, or increasing the antigen expression from a virus, gene or trans-gene expression from a virus, or virus protein expression in cells. Other uses, compositions and methods of using same are also provided.

Abstract: A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

Abstract: A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

Abstract: A medical device includes a clevis, a first blade, a second blade, and a tension member. The first and second blades are rotatably coupled to the clevis. The first blade includes a first coupling portion. The tension member is coupled to the first blade and applies a torque to the first blade to rotate the first blade about the clevis between a first, second, and third orientation. The second blade includes a second coupling portion. The second coupling portion is coupled to the first coupling portion such that A) the second blade remains in a fixed position relative to the clevis when the first blade is between the first and second orientation, and B) rotation of the first retractor blade between the second and third orientation transfers at least a portion of the torque to the second retractor blade causing rotation of the second blade about the clevis.

Abstract: Provided are methods for detecting protein interactions in a sample, the methods comprising: (a) detecting two or more polypeptides that when associated emit a first detectable signal in a first light emission spectrum; (b) contacting the two or more polypeptides with a third polypeptide conjugated to a dipole acceptor moiety that has a second light emission spectrum when excited within a light excitation spectrum, wherein the light excitation spectrum overlaps with the first light emission spectrum; and (c) detecting a second detectable signal emitted in the second light emission spectrum by the dipole acceptor moiety. Also provided are bioluminescent complexes comprising: (a) a first polypeptide conjugated to a dipole acceptor moiety, wherein the emits a first detectable signal in a first light emission spectrum.

Abstract: Techniques herein include processes and systems by which a reproducible CD variation pattern can be mitigated or corrected to yield desirable CDs from microfabrication patterning processes, via resolution enhancement. A repeatable portion of CD variation across a set of wafers is identified, and then a correction exposure pattern is generated. A direct-write projection system exposes this correction pattern on a substrate as a component exposure, augmentation exposure, or partial exposure. A conventional mask-based photolithographic system executes a primary patterning exposure as a second or main component exposure. The two component exposures when combined enhance resolution of the patterning exposure to improve CDs on the substrate being processed without measure each wafer.

Abstract: A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.