Patents by Inventor Jeffrey Smith

Jeffrey Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230078381
    Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.
    Type: Application
    Filed: August 5, 2022
    Publication date: March 16, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Lars LIEBMANN, Jeffrey SMITH, Daniel CHANEMOUGAME, Paul GUTWIN
  • Patent number: 11596401
    Abstract: A surgical stapler is provided that includes a first jaw and a second jaw. The first jaw includes a proximal end portion and a distal end portion. The second jaw includes a proximal end portion and a distal end portion. The proximal end portion of the first jaw is pivotally mounted to the proximal end portion of the second jaw. A flexible guide is secured to the distal end portion of the first jaw.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 7, 2023
    Assignee: Intuitive Surgical Operations, Inc.
    Inventor: Jeffrey A. Smith
  • Patent number: 11585078
    Abstract: A urinal screen can include a frame having: a first face; a second face opposite the first face; and a plurality of apertures extending through the first and second faces. The urinal screen can include a plurality of first posts extending from the first face of the frame and configured to at least partially dissipate splashing of urine that impacts the urinal screen; and a plurality of second posts extending from the second face of the frame and configured to at least partially dissipate splashing of urine that impacts the urinal screen; wherein: at least ? majority of the plurality of first and second posts are parallel to each other; at least ? of the plurality of second posts are parallel to each other; and the at least ? majority of the plurality of firsts posts extend at a non-perpendicular angle from with respect to the first face of the frame.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: February 21, 2023
    Assignee: Fresh Products, Inc.
    Inventors: Douglas S. Brown, Jeffrey A. Smith
  • Patent number: 11581242
    Abstract: A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 14, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith, Paul Gutwin
  • Patent number: 11574845
    Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 7, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Publication number: 20230031222
    Abstract: A system for processing cells is provided. The system can include a cell culture container, a fluid handling device, and one or more removable cell processing modules for performing one or more cell processing processes. The one or more removable cell processing modules can include a fluid handling pathway. The one or more removable cell processing modules can be fluidly connected to the cell culture container and the fluid handling device via a receptacle in which the cell processing modules may be inserted. The system can be a closed system.
    Type: Application
    Filed: September 23, 2022
    Publication date: February 2, 2023
    Inventors: Myo Thu MAUNG, Matthew Everly FOWLER, Paul DABROWSKI, Sergey SHKAPOV, Ivan RAZINKOV, Jingling LI, Daniel SLOMSKI, Jeffrey SMITH, James Duncan BRAZA, Aliya KUSUMO, Brandon Phillip WHITNEY
  • Publication number: 20230036597
    Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 2, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Daniel CHANEMOUGAME, Lars LIEBMANN, Paul GUTWIN, Subhadeep KAL, Kandabara TAPILY, Anton DEVILLIERS
  • Publication number: 20230024975
    Abstract: A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 26, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Publication number: 20230017350
    Abstract: Aspects of the present disclosure provide a method of manufacturing a three-dimensional (3D) semiconductor device. For example, the method can include forming a target structure, the target structure including a lower gate region, an upper gate region, and a separation layer disposed between and separating the lower gate region and the upper gate region. The method can also include forming a sacrificial contact structure extending vertically from the bottom gate region through the separation layer and the upper gate region to a position above the upper gate region, removing at least a portion of the sacrificial contact structure resulting in a lower gate contact opening extending from the position above the upper gate region to the bottom gate region, insulating a side wall surface of the lower gate contact opening, and filling the lower gate contact opening with a conductor to form a lower gate contact.
    Type: Application
    Filed: June 9, 2022
    Publication date: January 19, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Daniel CHANEMOUGAME, Lars LIEBMANN, Jeffrey SMITH, Paul GUTWIN
  • Patent number: 11545497
    Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 3, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith
  • Publication number: 20220416048
    Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 29, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Lars LIEBMANN, Daniel CHANEMOUGAME, Paul GUTWIN, Kandabara TAPILY, Subhadeep KAL, Robert CLARK
  • Patent number: 11532708
    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 20, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Publication number: 20220387841
    Abstract: System for mechanically assisting rehabilitation of a patient. The system includes: a manipulator having at least five degrees of freedom and defining a free end; a limb support for supporting a limb of the patient, and secured relative to the free end of the manipulator; a force sensor operatively connected to the limb support to allow measuring input forces applied by the patient; and a processor communicatively connected to the force sensor, the manipulator, and a memory store which defines a scale factor. The processor is configured to control operation of the manipulator to move the limb support, and further configured so that responsive to receiving an input force measurement from the force sensor, the processor determines an applied force as a function of the input force and the scale factor.
    Type: Application
    Filed: October 20, 2020
    Publication date: December 8, 2022
    Applicant: Tech Gym Pty Ltd
    Inventors: Dang LÊ MINH, Rowan JEFFREY SMITH
  • Patent number: 11517810
    Abstract: An arrow golf system has a bow having a bowstring, an arrow having a shaft with a ball on one end with a fletching and a string nock on an opposite end, a starting location, a finishing location, and a capturing apparatus at the finishing location. A player shoots the arrow from the starting location with the bow, to a second location closer to the finishing location, retrieves the arrow at the second location, and shoots the arrow toward the capturing apparatus from the second location.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: December 6, 2022
    Inventors: Woodrow W Clark, III, Jeffrey Smith
  • Patent number: 11510554
    Abstract: Reversibly attachable pressure-resistant cap for an endoscope sleeve, configured to seal a distal tip of the endoscope sleeve during pressurized inflation of the sleeve to assist insertion of the endoscope into the sleeve. The cap is operable to latch onto the distal tip. The cap is also configured to be easily removed from the distal tip after inflation is no longer needed.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 29, 2022
    Assignee: Motus GI Methical Technologies Ltd.
    Inventors: Brad D. Aurilia, Brad William Caldeira, Mark Pomeranz, Andy Scherer, Jeffrey Smith
  • Publication number: 20220375921
    Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.
    Type: Application
    Filed: August 3, 2022
    Publication date: November 24, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Anton deVilliers
  • Publication number: 20220367461
    Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 17, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Daniel CHANEMOUGAME, Lars LIEBMANN, Jeffrey SMITH, Paul GUTWIN
  • Patent number: 11495540
    Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 8, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton deVilliers
  • Patent number: 11488947
    Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 1, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Anton deVilliers
  • Publication number: 20220340573
    Abstract: Provided herein are compounds and pharmaceutical compositions useful for treating meibomian gland dysfunction (MGD), comprising administering to a subject in need thereof a therapeutically effective amount of a compound of Formula (I) or a compound of Formula (I?), or pharmaceutical composition described herein.
    Type: Application
    Filed: June 6, 2022
    Publication date: October 27, 2022
    Inventors: Kelly D. BOSS, Yi FAN, Alec Nathanson FLYER, Declan HARDY, Zhihong HUANG, Kathryn Taylor LINKENS, Jon Christopher LOREN, Fupeng MA, Valentina MOLTENI, Duncan SHAW, Jeffrey SMITH, Catherine Fooks SOLOVAY