Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.

Abstract: In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the polysilicon layer with holes in a gate region and pillars in a source region enables the channel zone to be doped more lightly. In another embodiment, the novel method is used for a channel width shading of a PMOS transistor cell.

Abstract: The invention relates to a circuit arrangement having connecting terminals (K1, K2) for application of a supply voltage (V+) and having a load transistor (M) for connecting a load (Z) to the supply voltage, said load transistor having a control terminal (G) and a first and second load terminal (D, S), the control terminal (G) of the load transistor (2) being coupled to a drive terminal (IN) for application of a drive signal (Sin). A voltage limiting circuit (10) is connected between one (D) of the load terminals and the drive terminal (G) of the transistor, a deactivation circuit (20) being provided, which is designed to deactivate the voltage limiting circuit (10) in a manner dependent on the supply voltage (V+).

Abstract: A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a phase-changeable or ovonic material. A heating device is disposed to heat the memory material at different rates to a programming temperature. The memory material either has a high resistance or a low resistance after cooling, depending on the heating rate. The heating device has a switching device and a heating element in immediate vicinity to the memory material. The switching device has a field-effect transistor and a drain region of the field-effect transistor forms the heating element. Alternatively, the heating element includes a diode or a diode chain.

Abstract: A MOS field effect transistor having a vertical source, drain and gate structure, the gate electrode of which has a dimensioning that determines the gate-drain capacitance (Miller capacitance) and provides a reduced capacitance.

Abstract: A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further regions of the second conductivity type surround the zone of the second conductivity type like a well. The further regions are interrupted in at least one location by a channel that is formed by the semiconductor body. The further regions are doped with a doping concentration that is high enough so that the further regions are not completely depleted of charge carriers when the semiconductor element is revere-biased.

Abstract: The present invention relates to a semiconductor component arrangement having the following features: a semiconductor substrate (10) of a first conduction type, an insulation layer (20) arranged on the substrate (10), a semiconductor layer (30) arranged on the insulation layer (20), there being formed in said semiconductor layer a semiconductor component with at least a first semiconductor zone (40) of a first conduction type, a second semiconductor zone (70) of a second conduction type, which adjoins the first semiconductor zone (40), and a third semiconductor zone (80), which is doped more heavily than the second semiconductor zone, at a distance from the first semiconductor zone (40), featuring at least one fourth semiconductor zone (90) of the second conduction type, which has a first section (91) formed in the second semiconductor zone (70) and a second section (92) formed in the underlying substrate (10), which sections are electrically conductively connected to one another through the insulation

Abstract: The invention relates to a method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features: a semiconductor body (100) having a first side (101) and a second side (102), a drift zone (30) of a first conduction type which is arranged in the region between the first and the second sides (101, 102) and is formed for the purpose of taking up a reverse voltage, a field electrode arrangement arranged in the drift zone (30) and having at least one electrically conducted field electrode (40; 40A-40E; 90A-90J) arranged in a manner insulated from the semiconductor body (100), an electrical potential of the at least one field electrode (40; 40A-40E; 90A-90J) varying in the vertical direction of the semiconductor body (100) at least when a reverse voltage is applied.

Abstract: The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

Abstract: The controllable semiconductor switching element blocks in both directions. The semiconductor switching element is formed with a first conduction region and a second conduction region of a first type of conductivity, a blocking region of a second type of conductivity which is disposed between the first and second conducting regions, and a control electrode which is arranged opposite the blocking region and insulated from it. A recombination region is configured in the blocking region and is comprised of a material that promotes a recombination of charge carriers of the first and second type of conductivity.

Abstract: A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the semiconductor body in the drift zone. The compensation zone is doped complementarily to the drift zone and connected by at least one connecting zone to a channel zone, which is doped complementarily to the drift zone and isolates the drift zone from a first terminal zone of the same conductivity type as the drift zone. A control electrode is formed in a manner insulated from the channel zone.

Abstract: A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least one zone of a second conductivity type, opposite to the first conductivity type, is embedded. Regions of the second conductivity type are provided in the semiconductor body in a plane running substantially parallel to the surface of the surface region. The regions are in this case sufficiently highly doped that they cannot be depleted of charge carriers when a voltage is applied.

Abstract: The present invention relates to a semiconductor component. The component includes a semiconductor body with a first semiconductor layer of a first conduction type and a second semiconductor layer of a second conduction type. The component includes, in the second semiconductor layer, a first terminal zone of the second conduction type, a drift zone of the second conduction type, a channel zone of the first conduction type, which is formed between the first terminal zone and the drift zone, and a second terminal zone of the second conduction type, which is arranged at a distance from the channel zone in the lateral direction of the semiconductor body. The component also includes a first drive electrode and at least one second drive electrode.

Abstract: A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the semiconductor body, and a drift path that is formed between the channel zone and the first connection zone and contains a compensation zone. The compensation zone has a complementary conduction type with respect to the drift zone and includes at least two segments. A distance between the two adjacent segments is chosen such that the punch-through voltage between these segments lies in a voltage range that corresponds to the voltage range assumed by the voltage drop across the drift path at currents situated between the rated current and twice the rated current.

Abstract: The invention relates to a MOSFET circuit having reduced output voltage oscillations, in which a smaller CoolMOS transistor (T2) with a zener diode (Z1) connected upstream of its gate is located in parallel with a larger CoolMOS transistor (T1), so that, during a switch-off operation, after the larger transistor has been switched off, the smaller transistor (T2) carries a tail current on account of the zener voltage still present, which tail current attenuates output oscillations of the voltage.

Abstract: A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second layer of the first conduction type lying above the first layer. The semiconductor component also has a first terminal zone that can be contact-connected at the first surface of the semiconductor body. The first terminal zone is formed in the second layer. A channel zone of a second conduction type surrounds the first terminal zone. Compensation zones of the second conduction type that are formed in the second layer are provided. Additionally, the semiconductor component has a second terminal zone of the first conduction type that can be contact-connected at the first surface of the semiconductor body. The second terminal zone is formed in the second layer.

Abstract: In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends away from a semiconductor body and forms a body region. A filling insulator surrounds the semiconductor pillar and is situated on the semiconductor body for insulating the MOSFET.

Abstract: A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is located above the substrate. A channel zone of the first conduction type is formed in the first layer. A first terminal zone of the second conduction type is configured adjacent the channel zone. A second terminal zone of the first conduction type is formed in the first layer. Compensation zones of the first conduction type are formed in the first layer. A second layer of the second conduction type is configured between the substrate and the compensation zones.

Abstract: A semiconductor component includes a semiconductor body of a first conductivity type which accommodates a space charge region. Semiconductor regions of a second conductivity type are disposed in at least one plane extending essentially perpendicularly to a connecting line extending between two electrodes. A cell array is disposed under one of the electrodes in the semiconductor body. At least some of the semiconductor regions of the second conductivity type are connected to the cell array via filiform semiconductor zones of the second conductivity type in order to expedite switching processes. A method for fabricating such a semiconductor component is also provided.

Abstract: A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is located above the substrate. A channel zone of the first conduction type is formed in the first layer. A first terminal zone of the second conduction type is configured adjacent the channel zone. A second terminal zone of the first conduction type is formed in the first layer. Compensation zones of the first conduction type are formed in the first layer.