Abstract: A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further regions of the second conductivity type surround the zone of the second conductivity type like a well. The further regions are interrupted in at least one location by a channel that is formed by the semiconductor body. The further regions are doped with a doping concentration that is high enough so that the further regions are not completely depleted of charge carriers when the semiconductor element is revere-biased.

Abstract: The invention relates to a two-chip power IC, in which a sensor chip having a sensor is mounted on a switch chip having a switch. The sensor is electrically connected to the switch in order to turn the switch off when a temperature detected by the sensor exceeds a threshold value which can be preset. In order to ensure that the sensor chip is heated more quickly, at least one supply line for the switch is routed in the vicinity of the sensor so as to assure good heat transfer from the supply line to the sensor.

Abstract: The SOI-FET has source and drain zones of one conductivity type arranged on an insulator. A semiconductor zone of another conductivity type (“body”) is arranged between the source and drain zones. A trench is introduced into the semiconductor zone of the other conductivity type. The trench is filled with an electrode material, which is capacitively or directly coupled to the semiconductor zone of the other conductivity type.

Abstract: A gate-controlled thyristor in which an IGBT in a first cell and a thyristor in a main cell are connected together in ouch a way that the first cell and the main cell form a lateral FET with a channel of a first conducting type. In an emitter zone of the thyristor, there is a layer embedded that increases the charge carrier recombination in order to reduce the start-up resistance of the gate-controlled thyristor. Trenches, filled with insulated gate electrodes, can be introduced into the lateral FET, so that the FET is a side wall FET.

Abstract: A method for forming a field effect vertical bipolar transistor that includes a semiconductive body that has at its top surface a plurality of emitter zones of one conductivity type, each surrounded by a base zone of the opposite conductivity type, and gate electrodes for creating a channel at the surface through the base zone into the bulk inner portion of the one conduction type and at a bottom surface a collector zone that includes a collector electrode overlying a collector layer of the opposite conduction type overlying a field stop layer heavily doped of the opposite conduction type overlying the inner portion lightly doped of the one conduction type. Each of the collector layer and the field stop layer is less than 2 microns in thickness and the collector layer is used to inject minority carriers into the inner zone when appropriately biased.

Abstract: A circuit configuration for driving an ignition coil includes a first semiconductor switch having a load path connected in series with a primary winding of the ignition coil, and having a control electrode, which is driven in accordance with a first drive signal. The circuit configuration further includes a second semiconductor switch having a load path connected in parallel with the primary winding and having a control electrode, which is driven in accordance with a second drive signal.

Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.

Abstract: A temperature-protected semiconductor circuit configuration that has an integrated switching unit. The switching unit is formed of a semiconductor switch, a first integrated temperature sensor for driving the semiconductor switch when an over-temperature is reached, first and second connecting terminals for connecting a load, and a control terminal for applying a drive signal for the semiconductor switch. A second temperature sensor is connected in a heat-conducting manner to the switching unit which exhibits at least one output terminal for providing a temperature-dependent temperature signal.

Abstract: A method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components includes producing a semiconductor wafer from a semiconductor substrate, on one outer surface of which a plurality of epitaxial layers are provided. Trenches and a marking groove, which reaches the semiconductor substrate, are introduced into the epitaxial layers. A polycrystalline silicon layer, which is doped with a dopant of one conduction type, is deposited on the surface of the uppermost epitaxial layer, the trenches and the marking groove. The surface of the uppermost epitaxial layer, which is provided with the doped polycrystalline silicon layer, is direct-bonded with an outer surface of a further semiconductor wafer provided with an insulating layer. The semiconductor substrate is removed from its other outer surface. Further trenches are introduced into the lowermost epitaxial layer from the removed surface until the bottom of the trenches is reached.

Abstract: A field-effect-controllable, vertical semiconductor component, and a method for producing the semiconductor component include a semiconductor body having at least one drain zone of a first conduction type, at least one source zone of the first conduction type, at least one gate electrode insulated from the entire semiconductor body by a gate oxide, and a bulk region of the first conduction type. A source terminal is located on the rear side of the wafer, and a drain terminal and a gate terminal are located on the front side of the wafer.

Abstract: A method for making contact with a covered semiconductor layer through a contact hole, includes producing a contact hole in an insulator layer for making contact with at least one covered semiconductor layer. A heavily doped polysilicon layer is produced on the surface of the insulator layer and the contact hole is at least partially filled with heavily doped polysilicon. A metal layer is applied on the heavily doped polysilicon layer for establishing an ohmic connection to the outside. A semiconductor component fabricated according to the method is also provided.

Abstract: The invention relates to an edge structure and a drift region for a semiconductor component. A semiconductor body of the one conductivity type has an edge area with a plurality of regions of the other conductivity type embedded in at least two mutually different planes. Underneath an active zone of the semiconductor component the regions are connected over different planes via connection zone, but the regions are otherwise floating.

Abstract: A power semiconductor component that can be controlled by a field effect has a multiplicity of parallel-connected individual components disposed in cells, the cells are disposed tightly packed on a relatively small space in a cell array. Parallel-connected source zones of the cells have shadowed regions that in each case reduce an effective W/L channel ratio in the cells containing the shadowed regions. The invention has the advantage that because of the provision of the shadowed regions inside the source zones that are preferably undoped or at least doped much weaker than the source zones, the critical regions in the cell array with the highest current density are specifically moderated. Thus the current density in the current-carrying filament of the cell is more homogeneously distributed. This measure renders it possible to reduce the cell grid spacing of the cells in the cell array, or to reduce the forward resistance per unit area, and this leads simultaneously to a reduction in the power loss.

Abstract: An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulator layer by a semiconductor region, which is doped with the dopant of the first conduction type that has been diffused out of the polycrystalline zone. A dopant source having a dopant of a second conductivity type is also provided. A zone having the dopant of the second conductivity type is formed by diffusing the dopant out of the dopant source.

Abstract: The semiconductor component, such as a Schottky diode with a low leakage current, has a metal-semiconductor junction between a first metal electrode and the semiconductor. The semiconductor, which is of a first conductivity type, has a defined drift path and a plurality of supplementary zones of a second conductivity type extending from the semiconductor surface into the drift path. A number of foreign atoms in the supplementary zones is substantially equal to a number of foreign atoms in intermediate zones surrounding the supplementary zones and the number of foreign atoms does not exceed a number corresponding to a breakdown charge of the semiconductor.

Abstract: A circuit configuration for pulsed current regulation of inductive loads includes a freewheeling configuration which is connected in parallel with the inductive load and has a current-measuring device in order to measure current exclusively while a switching device is in an open state. This avoids an otherwise customary shunt resistor and associated power loss.

Abstract: A voltage source provides an input signal to a drive circuit for a power semiconductor. A protective circuit is connected between the drain and the source of the power semiconductor and is activated when excess current is present. The protective circuit provides an output signal that is received by a control circuit to limit the voltage at the gate of the power semiconductor. The control circuit is connected between the gate and the source. A controllable resistance including an enhancement MOSFET and an external capacitor in which the enhancement MOSFET has a gate, a source and an internal capacitance between the gate and the source is connected in parallel to the external capacitance. The controllable resistance carries the input signal from the voltage source to the power semiconductor. The controllable resistance is switched to high impedance when the protective circuit is activated and switched to low impedance when the protective circuit is deactivated.

Abstract: A high-voltage SOI thin-film transistor includes a semiconductor thin film of a first conductivity type which is embedded in an insulator layer disposed on a semiconductor body. The semiconductor thin film includes a drain zone and a source zone, both having a second conductivity type opposite the first conductivity type. A gate electrode is also provided in the insulator layer. Field plates are disposed obliquely in the insulator layer between the gate electrode and the drain zone, in such a way that their spacing from the semiconductor thin film increases with increasing distance from the gate electrode. Highly doped zones of the second conductivity type in the semiconductor thin film are associated with the field plates, so that when a space charge zone is propagating from the source zone, a voltage at the various field plates stops changing and remains the same.

Abstract: A silicon-on-insulator insulated gate bipolar transistor (SOI-IGBT) has a channel zone of a first conductivity type, at least one cell zone of a second conductivity type, and at least one intermediate zone of the first conductivity type which delimits the SOI-IGBT. The channel zone, the cell zone, and the intermediate zone are disposed in an insulator layer, which is provided on a semiconductor body of the first conductivity type. The channel zone, the cell zone, and the intermediate zone are connected to the semiconductor body via openings provided in the insulator layer. A semiconductor configuration having a CMOS circuit integrated with an SOI-IGBT is also provided.

Abstract: The invention relates to a method for bonding two wafers, in which the wafers are placed over one another in such a way that a first surface of one wafer lies over a first surface of the other wafer. Trenches are introduced into at least one of the first surfaces. The trenches run in the plane of the surfaces. The wafers lying one on top of the other are then subjected to a heat treatment in an oxidizing atmosphere.