Abstract: The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.

Abstract: A semiconductor module includes a housing with at least one semiconductor component that is conductively connected to at least one output line. An integrated temperature sensor is also housed in the housing. This sensor is connected, via at least one of its load terminals, to a terminal for receiving a supply potential. The temperature sensor conducts a load current that heats-up the temperature sensor when a first temperature threshold is crossed and a supply potential is in being supplied. A housed interruption device is arranged in such a way that it interrupts the output lines carrying the load current when a second temperature threshold has been exceeded.

Abstract: The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.

Abstract: A temperature-protected semiconductor circuit configuration that has an integrated switching unit. The switching unit is formed of a semiconductor switch, a first integrated temperature sensor for driving the semiconductor switch when an over-temperature is reached, first and second connecting terminals for connecting a load, and a control terminal for applying a drive signal for the semiconductor switch. A second temperature sensor is connected in a heat-conducting manner to the switching unit which exhibits at least one output terminal for providing a temperature-dependent temperature signal.

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: The invention relates to an integrated semiconductor switching element, that includes a semiconductor body having a first connection zone of a first conduction type and a second connection zone of the first conduction type. A body zone of a second conduction type is located in the semiconductor body. The body zone is located between the first connection zone and the second connection zone. A control electrode is located alongside the body zone and is insulated from the semiconductor body. A Schottky barrier is located on the second connection zone. A first connection electrode is electrically conductively connected to the first connection zone and to the Schottky barrier. The invention also relates to a process for producing a semiconductor switching element.

Abstract: The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain voltage and a positive gate voltage are applied. A current that can be controlled with the gate voltage flows in the inversion channels.

Abstract: The semiconductor component can be controlled by the field effect and it blocks in both directions. The component has a semiconductor body with a first connecting zone, a second connecting zone and a channel zone formed between the first and the second connecting zone. A control electrode is formed adjacent to the channel zone such that it is isolated from the semiconductor body. In order to avoid a reduction in the withstand voltage due to a parasitic bipolar transistor, a recombination zone, which is formed from a material that assists the recombination of charge carriers of the first and second conductivity types, is formed in the channel zone and the second connecting zone.

Abstract: A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the semiconductor body in the drift zone. The compensation zone is doped complementarily to the drift zone and connected by at least one connecting zone to a channel zone, which is doped complementarily to the drift zone and isolates the drift zone from a first terminal zone of the same conductivity type as the drift zone. A control electrode is formed in a manner insulated from the channel zone.

Abstract: A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones of a second, opposite conductivity type are embedded in the interface region between the semiconductor substrate and the at least one layer. The floating semiconductor zones are dimensioned such that the dimension of a semiconductor zone is do small compared to the layer thickness of the at least one semiconductor layer and is essentially equal to or less than a distance between the floating semiconductor zones in the interface region.

Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.

Abstract: A voltage transformer includes a pair of input terminals for applying an input voltage, a series circuit connected in parallel to the pair of input terminals of a first switch, and a low pass filter. The low pass filter has output terminals for connecting a load. A freewheeling circuit is connected in parallel to the low pass filter. The freewheeling circuit has a second switch, which is configured as a MOS transistor, with a gate terminal and a load path formed between a first load path terminal and a second load path terminal. The MOS transistor has a body zone mounted in a floated manner or connected to a source zone by an ohmic resistor.

Abstract: The semiconductor component has a circuit configuration for driving an electrical load. The circuit includes a control circuit with a power switch driven by a drive configuration and feeding a current to the load. The semiconductor component has a first temperature detector thermally closely coupled to the power switch and a further temperature detector. A temperature evaluation circuit receives temperature signal from the temperature detectors and generates a signal that depends on the signals of the temperature detectors and feeds the signal to the drive configuration.

Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.

Abstract: A voltage transformer includes a pair of input terminals for applying an input voltage, a series circuit connected in parallel to the pair of input terminals of a first switch, and a low pass filter. The low pass filter has output terminals for connecting a load. A freewheeling circuit is connected in parallel to the low pass filter. The freewheeling circuit has a second switch, which is configured as a MOS transistor, with a gate terminal and a load path formed between a first load path terminal and a second load path terminal. The MOS transistor has a body zone mounted in a floated manner or connected to a source zone by an ohmic resistor.

Abstract: The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain zone, together with the source zone and drain zone, extend to an n-conductive substrate. The source zone and the drain zone are surrounded by a p-conductive area.

Abstract: A low impedance VDMOS semiconductor component having a planar gate structure is described. The VDMOS semiconductor component contains a semiconductor body of a first conductivity type having two main surfaces, including a first main surface and a second main surface disposed substantially opposite to one another. A highly doped first zone of the first conductivity type is disposed in an area of the first main surface. A second zone of a second conductivity type separates the first zone from the semiconductor body. The first zone and the second zone have a trench with a bottom formed therein reaching down to the semiconductor body. An insulating material fills the trench at least beyond an edge of the second zone facing the semiconductor body. A region of the second conductivity type surrounds an area of the bottom of the trench.

Abstract: The invention relates to a source-down power transistor, in which narrow trenches filled with insulated polysilicon are provided between a source pillar and a drain pillar. Inversion channels form on the side walls of the trenches when a positive drain voltage and a positive gate voltage are applied. A current that can be controlled with the gate voltage flows in the inversion channels.

Abstract: In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends away from a semiconductor body and forms a body region. A filling insulator surrounds the semiconductor pillar and is situated on the semiconductor body for insulating the MOSFET.

Abstract: A lateral high-voltage sidewall transistor configuration includes a low-doped semiconductor substrate of a first conductivity type and a low-doped epitaxial layer of a second conductivity type disposed on the semiconductor substrate. First semiconductor layers of the first conductivity type and second semiconductor layers of the second conductivity type are disposed in an alternating configuration in the epitaxial layer. A source region and a drain region of the second conductivity type extend through the first and second semiconductor layers as far as the semiconductor substrate. A gate electrode includes a gate insulating layer lining a gate trench and includes a conductive material which fills the gate trench. The gate electrode extends through the first and second semiconductor layers as far as the semiconductor substrate and is disposed adjacent to the source region toward the drain region.