Abstract: On the semiconductor body of a MOSFET (1), the semiconductor body of a thyristor (5) (or of a bipolar transistor) is located for thermal conduction purposes. The anode and cathode terminals (A, K) (emitter and collector terminal) are connected to the gate terminal (G) and to the source terminal (S) of the MOSFET (1), respectively. The thyristor (bipolar transistor) is rated so that it turns on before a temperature of 150.degree. to 180.degree. is obtained which is critical for the MOSFET. Thus the gate-source capacitance of the MOSFET is effectively shortcircuited and the MOSFET turns off.

Abstract: A field effect controllable bipolar transistor or isolated gate bipolar transistor (IGBT) has a drastically reduced inhibit delay charge, given identical on-state behavior, in that the anode zone has a thickness of less that 1 micrometer, it is doped with implanted ions with a dose of about 1.times.10.sup.12 through 1.times.10.sup.15 cm.sup.-2, and in that the life time of the minority charge carriers in the inner zone amounts to at least 1 microsecond.

Abstract: A circuit for monitoring the temperature of a semiconductor structural component. The circuit includes a bipolar transistor (1) in thermal contact with a semiconductor structural element to be monitored, and a MOSFET (11) connected in series with a current source (12). The MOSFET (11) is maintained in a nonconducting state with two Zener diodes (13, 14) if the bipolar transistor (1) is the standard operating temperature of the semiconductor structural element. This circuit provides for a reduced zero current signal. The current flowing through the bipolar transistor (1) increases with temperature and the gate-source voltage of the MOSFET (11) is increases until it switches off. If the current flowing through the MOSFET (11) is greater than the impressed current of the current source (12) the potential across the current source takes a step increase a value near the supply voltage (V.sub.DD). This voltage step can then be detected as an excess-temperature signal.

Abstract: A power FET is driven by a photodiode chain across a switch, which has two FETs (5, 6) arranged in series. Upon illumination the first FET (5) is driven to be conducting, which permits current to flow from a capacitor (C) connected to a fixed voltage into the gate-source capacitor (C.sub.GS) of the power FET (1) and to switch it on rapidly. Upon cessation of the illumination, the first FET (5) is blocked while the second FET (6) is driven to be conducting. Hence, the C.sub.GS of the power FET is discharged and the power FET is blocked.

Abstract: A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).

Abstract: In a circuit for driving a MOSFET connected to a load on the source terminal, the MOSFET is configurated as a source follower that is driven by a voltage doubling circuit including two diodes (D1, D2) serially connected together. The drain terminal of the MOSFET is connected to the operating voltage source and its gate terminal to the voltage doubling circuit which includes a capacitor (C). One terminal of the capacitor is connected between the diodes and its other terminal is supplied with a clocked dc voltage. The first diode (D2) is formed by a lateral MOSFET, whose gate electrode is connected with the drain zone. The second diode is formed by a vertical bipolar transistor with low current gain. A resistor is located between the emitter zone and the source zone. This particular circuit geometry is readily suitable for realization in integrated form.

Abstract: The temperature of the power semiconductor component is sensed by a bipolar transistor. The bipolar transistor is in series with a depletion mode MOSFET whose gate and source electrodes are connected together. The drain electrode is also connected to a threshold element. Normally, the FET has low impedance, so that at the input of the threshold element source potential, e.g. ground potential, is present. With current rising as a function of temperature, the current through the FET is limited to a constant, essentially temperature-independent value, and the potential at the input of the threshold element rises steeply. This condition is detected as an overtemperature signal.

Abstract: The voltage peaks occuring upon disconnection of inductive loads are normally attenuated by a by-pass diode connected in parallel with the load. The driving countervoltage is thereby limited to the value of the forward voltage drop of the diode. For a power MOSFET with a source-side inductive load, the driving countervoltage is increased by placing a series connection of an additional MOSFET and a Zener diode between the gate of the power MOSFET and the connection of the load which is remote from the power MOSFET. The driving countervoltage at the source now becomes the Zener voltage plus the occuring gate-source voltage of the power MOSFET.

Abstract: When a power MOSFET operated as a source follower is driven by an electronic switch, an interruption of the connection between ground and the electronic switch may result in the output potential of the electronic switch to change so that the power MOSFET is partially switched on. This causes a considerable amount of power dissipation. Therefore, there is placed between the source and gate electrodes of the MOSFET a depletion MOSFET whose gate is connected to the terminal of the electronic switch intended for connection to ground. Thus, the power MOSFET remains non-conducting upon interruption of the connection between the electronic switch and ground.

Abstract: In a circuit arrangement having a phototransistor, in order to increase the inverse voltage strength of the phototransistor, a resistor that carries off the collector-base inverse current generally lies between the base zone and the emitter zone of the phototransistor. This resistor should be as large as possible given illumination in order to increase the current gain. The resistor according to the invention is formed by the drain-source path of an IGFET of depletion type whose gate terminal is at a fixed potential. The IGFET is conductive in the unilluminated condition of the phototransistor. During illumination, its resistance increases given an increasing photocurrent.

Abstract: A switching circuit includes two series-connected MOSFET (1, 6) complementing one another, which are interconnected at the drain terminal of each device. The gate terminal of the MOSFET that is grounded is connected to a control input terminal (E). This gate terminal is also connected to the source terminal of a depletion FET (7). The drain terminal of the depletion FET (7) is connected to the gate terminal of the second MOSFET (6) and, in turn, is connected via a resistor (8) to a voltage source (+U). The gate terminal of the depletion FET (7) is grounded. The load (5) is then connected to the drain side of the complementary MOSFET. When the switch is in a blocking condition, the cross current is thus prevented from flowing; and the FET connected to voltage can be completely activated.

Abstract: A dynamic semiconductor memory cell has a field effect transistor and a memory capacitor formed on a semiconductor body. In addition to a first zone, doped oppositely with respect to the doping of the semiconductor body, further zones are formed parallel to the boundary surface of the body and doped with the same conductivity of the semiconductor body, but to a higher degree. The further zones lie below regions at the boundary surface which are doped opposite to the semiconductor body. The further zones include edge portions which extend up to the boundary surface and which limit the regions thereabove in the lateral direction. A gate is provided and in an area of the semiconductor body beneath the gate and adjacent to the boundary surface a region is provided, doped opposite to the semiconductor body and connecting the edge portions. The edge portions, at the boundary surface, form a two-part channel area of the field effect transistor.

Abstract: In a circuit arrangement for drive of a thyristor with a phototransistor, the collector-emitter path of the phototransistor is between one of two alternating voltage terminals and a gate terminal of the thyristor. In order to prevent an activation of the unilluminated phototransistor due to a steep voltage edge (dv/dt) load), its base current given such a load is carried off via an IGFET of the enhancement type. This IGFET is controlled by an IGFET of the depletion type acting as a current source which lies between a gate terminal and source terminal of the enhancement type IGFET. A capacitor is connected in series with the depletion-type IGFET. This series connection lies between the two alternating voltage terminals.

Abstract: A MIS field effect transistor of the depletion type having source, drain and channel regions of a first conductivity type formed in a substrate of the second conductivity type. A gate electrode is formed on an insulating layer above the channel. The spacing between the channel and the gate electrode increases between the source and the drain. This increase in spacing may be a continuous increase in the direction of the drain or may be a series of steps. A circuit arrangement is described where a plurality of these depletion MIS field effect transistors of the above type are serially connected with the source of the first of these depletion type transistors, connected to the drain of a preceding enhancement type MIS field effect transistor.

Abstract: A dynamic storage element has an electrically insulating layer carried on a substrate of semiconductor material. A conductor path, provided with a terminal, is arranged on the electrically insulating layer, and first and second zones, doped oppositely to the substrate, are provided on the surface of the substrate. The zones are spaced from one another. In that region of the substrate between the zones the substrate is more highly doped with dopants of the same type as those contained in the substrate and the conductor path extends above the highly doped region.

Abstract: A MIS field effect transistor having a source zone of a first impurity type formed in a semiconductor substrate immediately below one planar surface thereof, a drain zone of the first conductivity type in said substrate spaced from the source zone immediately below said one surface, a third zone, of said first impurity type in said substrate extending between said source and drain zones and extending deeper in said substrate than either said source or drain zones, a thin buried zone of the second conductivity type in said substrate spaced below and around the ends of said source zone, the region of said buried zone where it lies between said source and drain zones providing a channel whose length is only the thickness of the buried zone in the region where the buried zone reaches the substrate surface. A process for producing such a transistor is also disclosed.

Abstract: An opto-electronic sensor has an insulating substrate on which a plurality of x-lines of doped n (p) type conductivity semiconductor material are arranged. A light-permeable insulating layer covers the x-lines. A plurality of y-lines of electrically conductive material are then arranged over the insulating layer transversely to the x-lines. Sensor elements are formed at the crossover points of the x- and y-lines. A partial region of opposite conductivity type light sensitive material is arranged adjacent the x-line and beneath the y-line at the crossover point. This partial region forms a barrier-layer effect at a junction of the partial region with the doped semiconductor material of the x-lines.

Abstract: A field effect transistor with a MIS gate arrangement having a source and drain formed in a semiconductor body and including an electrically conductive region additionally provided which lies beneath the source zone and which has a conductivity opposite to and/or electrical conductivity which is higher than the semiconductor body which surrounds the zone and in which in the controllable field effect gate the electrically conductive zone is spaced a distance from the gate and the boundary surface and wherein the gate insulation layer projects laterally a space relative to the source zone which is approximately 1 to 10 times the thickness of the gate insulation layer and the distance from the gate arrangement to the boundary surface is 1 to 5 times the thickness.

Abstract: An integrated circuit formed on the surface of an insulating substrate is provided with an overlying conductive layer interconnecting the integrated circuit with an external electrode, and an intermediate layer of insulating material is interposed between the conductive layer and the substrate.

Abstract: A Schottky gate field effect transistor of the type comprising a silicon body of one conductivity type on an insulator substrate, and source, drain and gate electrodes is provided with a pn-junction located parallel to the surface of the substrate which produces a space charge zone occupying the zones of the silicon body close to the substrate surface, and a relatively thin active layer is located between the space charge zone and the gate electrode, the active layer having the same type conductivity as the silicon body.