Abstract: In a circuit arrangement for regulating the load current of a power MOSFET, the drain-source voltage of the power MOSFET is imaged onto the input of a second MOSFET connected between a gate terminal and source terminal of the power MOSFET. When the input voltage exceeds the cut-off voltage, then the gate-source voltage at the power MOSFET is regulated back to a value that corresponds to the sum of the cut-off voltages of the second MOSFET and a third MOSFET. The gate terminals of third MOSFET and the power MOSFET are connected to one another.

Abstract: A power semiconductor component assembly includes a power semiconductor component having a semiconductor body. A controllable switch is connected to the power semiconductor component. A temperature sensor has a given reset time. The temperature sensor is connected to the controllable switch for turning on the controllable switch to control the power semiconductor component from a conducting state into a range of higher resistance once a temperature in the semiconductor body of the power semiconductor component attains a critical value. A delay member is connected between the temperature sensor and the controllable switch. The delay member is triggered upon response of the temperature sensor and has a delay time being longer than the given reset time, for preventing blocking of the controllable switch during the delay time.

Abstract: MOSFET and IGBT components protected against overvoltage by a limiting diode inserted between drain or, respectively, collector terminal and gate terminal are provided. A freewheeling diode connected to the component having a limiting diode with a breakdown voltage that is lower than the breakdown voltage of the freewheeling diode by a defined amount is provided. This over-voltage protection can be achieved in a simple way by integrating the limiting diode into the semiconductor body of the freewheeling diode and by a corresponding arrangement of the anode zone of the limiting diode.

Abstract: The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.

Abstract: A MOSFET protection circuit includes a switch element which is thermally coupled to the MOSFET and switches the MOSFET off by establishing a connection between the gate and source electrodes thereof when a critical temperature is reached. The switch element also generates a temperature-dependent signal which controls a voltage reducing element connected between the gate and source electrodes of the MOSFET. The voltage reducing element is activated at a temperature which is lower than the critical temperature so that the gate-source voltage of the MOSFET and the current flowing therethrough is reduced as a result at the second temperature. The temperature rise is thereby slowed.

Abstract: A control circuit for an MOS semiconductor component having gate and source terminals has a load connected in series with the source terminal. A voltage source at fluctuating potential has first and second terminals. A first controllable semiconductor switch has a control input and is connected between the first terminal of the voltage source and the gate terminal of the MOS semiconductor component. The second terminal of the voltage source is connected to the source terminal of the MOS semiconductor component. A second switch is controllable by an input signal and has first and second load terminals. A line is connected to a fixed potential and to the first load terminal of the second switch. The second load terminal of the second switch is switched from a first to a second potential as a function of the input signal. The first and second potentials are between potentials of the first and second terminals of the voltage source.

Abstract: A power MOSFET includes a semiconductor body having first and second surfaces. An inner zone of a first conduction type has a given dopant concentration. At least one base zone of a second conduction type is adjacent the inner zone and the first surface. At least one source zone is embedded in the at least one base zone. At least one drain zone is adjacent one of the surfaces. Additional zones of the second conduction type are disposed in the inner zone inside a space charge zone developing when a blocking voltage is present. At least one additional zone of the first conduction type is disposed between the additional zones of the second conduction type and is doped higher than the inner zone. The additional zones have a dopant level and the additional zones of the second conduction type are mutually spaced apart, for depleting charge carriers when a blocking voltage is applied.

Abstract: An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.

Abstract: Power FETs having a load at the source side require a gate voltage lying above the drain voltage in order to be driven completely conductive. This can occur with a known pump circuit. In the drive circuit disclosed, the diode connected to the gate terminal of the power FET is a depletion FET whose substrate terminal is applied to the oscillating voltage that is required for the operation of the pump circuit. The cut off voltage is thus synchronously set relative to the oscillating voltage such that low losses arise when loading C.sub.GS and an adequately high inhibit voltage can be built up when loading the pump capacitor.

Abstract: A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between the first input terminal and the gate terminal of the first power FET. A second FET of the opposite channel type from that of the first power FET has a gate terminal and has drain and source terminals defining a drain-to-source path. A second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of the second FET to the drain terminal of the power FET. A resistor is connected between the gate and source terminals of the second FET. A controllable switch is connected to the gate terminal of the second FET. A second input terminal is connected to the controllable switch for receiving a voltage being lower than a supply voltage.

Abstract: A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.

Abstract: A circuit for detecting the non-operating condition of a load which is connected in series with an electronic switch wherein a comparator has a first input which is connected to the junction point between the load and the electronic switch and has a second input which is a reference voltage such that when the load fails the comparator produces an output to indicate such condition and wherein the reference voltage is lower than the normal voltage when the load is operating properly and is higher than when the load is in the inoperative condition.

Abstract: The gate-source capacitance of a power MOSFET (1) can be protected against positive and negative excess voltages by two integrated Zener diodes (3, 4) the anodes of which are coupled to each other and the cathodes of which are respectively coupled to the gate and source terminals of the power MOSFET. However, when a control voltage is applied, the parasitic bipolar transistor associated with one of the Zener diodes is switched on and prevents the MOSFET from completely switching on. The parasitic bipolar transistor is rendered harmless by the fact that the anode terminal is coupled to a source terminal (S) MOSFET (1) when a gate-source voltage is applied.

Abstract: In order to rapidly reduce the magnetic energy of an inductive load (2), the driving voltage must be high. When the load (2) is disconnected via a MOSFET (3), then a premature activation of the MOSFET (3) given reversal of the voltage at the inductive load (2) must be prevented. A series circuit of a Zener diode and of a controllable switch (3) is connected between the gate and the load (2). A current source (depletion MOSFET 5) whose current is lower than the current that would flow upon Zener breakdown is connected between the gate and the source of the power MOSFET (1). The MOSFET (3) becomes conductive upon Zener breakdown and the energy is quickly reduced by a high voltage, essentially by the Zener voltage.

Abstract: A bipolar transistor is disclosed including a semiconductor body having a cathode-side surface and an anode-side surface, and at least one insulated gate electrode. The semiconductor body has a central region with a predetermined doping concentration and of a first conductivity type. The central region borders on the cathode-side surface of the semiconductor body. Bordering on the cathode-side surface, at least one gate region is provided which borders on the central region. The gate region is of the second conductivity type and has a higher doping concentration than the central region. In the gate region, a source region is provided which borders on the cathode-side surface. The gate electrode is seated on an insulating layer applied on the cathode-side surface and covers the gate region. Between the anode-side surface and the central region is provided an anode region of the second conductivity type which has a higher doping concentration than the central region.

Abstract: The voltage (U.sub.DS) on a power MOSFET (1) is compared with a voltage (U.sub.V) derived from the sum of the voltages of a Zener diode (3) and the threshold voltage (U.sub.T) of a second MOSFET (5) to detect a short circuit in a load (2) in series with the power MOSFET (1). When this total voltage is exceeded, the second MOSFET conducts. Its load current is then evaluated as the short circuit signal.

Abstract: A thyristor is controlled by a phototransistor whose photo current is reduced by a MOSFET if the thyristor voltage surpasses a prescribed value. The MOSFET is controlled by two current supplies. The first current supply is connected between a gate terminal and a connecting terminal of the thyristor. The second current supply is connected between the gate and source of the MOSFET. The maximum current capacity of the first current supply is greater than the maximum current capacity of the second current supply.

Abstract: A power MOSFET composed of a plurality of individual MOSFETs connected in parallel, wherein an additional sensing MOSFET monitors the current in the power MOSFET. The sensing MOSFET has a surface comparatively smaller than the power MOSFET and is connected in parallel with the power MOSFET with a resistor between the source of the power MOSFET and the source of the sensing MOSFET. The sensing MOSFET and resistor are integrated with an integrated circuit provided for the control of the power MOSFET.

Abstract: A circuit arrangement for controlling load current of a power MOSFET wherein the load is connected at the source terminal includes a second FET having a defined threshold voltage connected with its drain-source path inserted between the gate and source of the power MOSFET. A third FET connects the gate terminal of the second FET to the drain voltage of the power MOSFET when the power MOSFET is in the conductive condition. When the drain-source voltage of the power MOSFET becomes higher than the threshold voltage of the second FET, the second FET becomes conductive and drives the gate-source voltage of the power MOSFET down.

Abstract: Semiconductor structural elements with four regions of alternating conductivity type have a stored charge characteristic which becomes apparent as so-called "tail" current upon switching off. The tail current can be reduced by means of an anode-side emitter region containing damaged regions generated by laser bombardment which extend through a pn-junction formed between the anode-side emitter region and a central region up into the central region.