Abstract: A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: A display device includes: a display panel divided into a first area and a second area; a first scan driver to provide a scan signal to a pixel in the first area through a first scan line coupled to the pixel in the first area; a second scan driver to provide the scan signal to a pixel in the second area through a second scan line coupled to the pixel in the second area; a first scan switching transistor and a second scan switching transistor to couple the first scan line to the second scan line based on the scan signal, the first scan switching transistor and the second scan switching transistor being arranged between the first area and the second area; a data driver to provide data signals; and a timing controller to control the first and second scan drivers and the data driver.

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract: Embodiments relate to a display device including: a first base substrate; gate lines disposed on the first base substrate, the gate lines extending in a first direction; parasitic capacitance electrodes coupled to the gate lines; data lines extending in a second direction crossing the first direction; transistors, each coupled to one of the gate lines and coupled to one of the data lines; and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and at least two drain electrodes among the drain electrodes of the transistors each overlap a corresponding one of the parasitic capacitance electrodes in different areas as viewed from a plan view.

Abstract: There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.

Abstract: A display device includes: a display panel having a display area and a non-display area; a plurality of pixels on the display area to emit light, wherein pixels arranged along a first direction are defined as first pixel groups and pixels arranged along a second direction are defined as second pixel groups; gate driving units on the display area to generate gate signals, wherein the gate driving units include first and second gate driving units corresponding one-to-one with each other; a data driver on the non-display area to generate data signals; a plurality of first lines to transmit the data signals to the plurality of pixels; and a plurality of second lines to transmit driving start signals from the first gate driving units to the second gate driving units respectively corresponding to the first gate driving units, wherein the first or second lines are between the first groups.

Abstract: The present invention relates to tricarbonyl technetium-99m or rhenium-188 labeled cyclic RGD derivatives, a preparation method thereof, and a pharmaceutical composition containing the derivative as an active ingredient for use in the diagnosis or treatment (radiotherapy) of angiogenesis-related diseases. The tricarbonyl technetium-99m or rhenium-188 labeled cyclic RGD derivatives of the present invention has a high subnanomolar affinity to integrin ?v?3 (also called as a vitronectin receptor) that is activated in an angiogenic action induced by a tumor, and acts exclusively upon cancer cells having selectively activated integrin ?v?3 because of a substantially low intake into the liver and intestines.

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N?1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

Abstract: A gate driving circuit includes a plurality of driving stages applying gate signals to gate lines of a display panel. Among the plurality of driving stages, a k-th (k being a natural number equal to or greater than 2) includes a first node, an output part that is connected to the first node and outputs a k-th gate signal in response to a voltage of the first node, a control part that controls an electric potential of the first node, an inverter part that outputs a k-th switching signal, and a pull-down part that receives a (k?1)th switching signal from a (k?1)th driving stage of the plurality of driving stages and lowers a voltage of the output part in response to the (k?1)th switching signal.

Abstract: A display device includes pixels, gate lines, and data lines on a substrate. The pixels include sub-pixels, and each sub-pixel includes a respective one of a plurality of first electrodes connected to one of the gate lines and one of the data lines. The first electrode of the sub-pixel at an n-th row and the first electrode of the sub-pixel at an (n+2)-th row in a same column are connected to different ones of the data lines. The sub-pixels in the n-th and (n+2)-th rows in the same column emit the same color of light.

Abstract: According to an embodiment, a display device includes a display panel including a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driver driving the plurality of gate lines, a data driver configured to output a plurality of data output signals to the plurality of data lines in response to a data signal, a demultiplexer circuit configured to provide the plurality of data output signals to the plurality of data lines in response to a first selectin signal and a second selection signal; and a timing controller configured to provide the data signal to the data driver, outputting the first selection signal and the second selection signal, and controlling the gate driver.

Abstract: A lithium secondary battery of the present invention may simultaneously improve high output and high capacity characteristics by including a first active material layer having high output characteristics and a second active material layer having high capacity characteristics respectively on a cathode collector and an anode collector.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A display device includes pixels arranged in a matrix form, gate lines extending in a first direction; data lines extending in a second direction, first and second unit pixel columns, each defined by adjacent data lines and the pixels connected thereto, first and second channels which transmit data signals to each of the first and second unit pixel columns, and a line selector which connects the first and second channels to the data lines and provides data voltages to the data lines in response to control signals, where a pixel connected to a first gate line is connected to a data line at a side thereof, a pixel connected to a second gate line is connected to a data line at the other side thereof, and each of the first and second channels is connected to a data line of each of the first and second unit pixel columns.

Abstract: A display apparatus includes gate lines configured to receive gate signals, data lines arranged to cross the gate lines and configured to receive data voltages, and pixels grouped into first pixel groups and second pixel groups and connected to the gate lines and the data lines. The gate signals are configured to be applied to the gate lines in a predetermined order while skipping at least one gate line without being sequentially and consecutively applied to two gate lines adjacent to each other among the gate lines.