Abstract: An electrophoretic display includes a display area where images are displayed, and an edge area around the display area and where a single color is displayed. The display area includes a plurality of display pixels which include gate lines on a first substrate, data lines intersecting the gate lines, thin film transistors connected to the gate lines and data lines, display pixel electrodes on the first substrate and connected to the thin film transistors, a common electrode on a second substrate and facing the first substrate, and an electronic ink layer between the display pixel electrodes and the common electrode The edge area includes a plurality of edge pixels which include edge pixel electrodes in a same shape as the display pixel electrodes.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: Disclosed is the synthesis of [18F]flumazenil that is useful in imaging epileptic lesions by PET (positron emission tomography). A method for preparing [18F]flumazenil by reacting a diaryliodonium salt precursor with the positron-emitting radionuclide fluorine-18. [18F]flumazenil can be prepared from the diaryliodonium salt precursor in the presence of kryptofix2.2.2./potassium carbonate(K2.2.2./K2CO3) and TEMPO in dimethylformamide (DMF) at a high yield.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: An exemplary embodiment of the present invention provides a liquid crystal display including: a first insulating substrate; a light blocking member positioned on the first insulating substrate and having a frame portion defining openings for pixels; a step compensated pattern positioned on the first insulating substrate and in one of the openings; a second insulating substrate facing the first insulating substrate; a first electrode formed on the first insulating substrate in the same layer as a second domain dividing unit; a second electrode facing the first electrode and disposed in the same layer as the first domain dividing unit; and a liquid crystal layer interposed between the first electrode and the second electrode, wherein the step compensated pattern overlaps the first domain dividing unit or the second domain dividing unit.

Abstract: A three-dimensional (3D) image display device includes data lines, gate lines crossing the data lines, sub-pixels arranged in areas between the data lines and the gate lines, a data driver that drives the data lines, a first gate driver that drives first gate lines from among the gate lines, a second gate driver that drives second gate lines from among the gate lines, and a timing controller that controls the data driver, the first gate driver, and the second gate drivers according to an image signal and a control signal. The second gate driver does not drive the second gate lines during a 3D display mode.

Abstract: A contents management method and apparatus of a mobile terminal provides improved security of private contents. A contents management method of a mobile terminal includes establishing a connection to at least one external terminal. The method also includes segmenting a content stored in the mobile terminal into segments and sharing the content by distributing the segments to the terminals. The method further includes integrating the segments distributed to the terminals into the content when a content execution command is input. The method still further includes storing the integrated content and deleting the integrated content in the mobile terminal when at least one of the terminals is disconnected.

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract: A display apparatus includes a display panel including a plurality of pixel columns to display an image, wherein each of the pixel columns includes a plurality of pixels arranged in a first direction and sequentially turned-on in the first direction; a gate driver disposed on the display panel and including a plurality of stages connected to the pixels to sequentially apply a gate signal to the pixels, where at least two stages of the stages are disposed adjacent to each other in a second direction different from the first direction; and a data driver which applies a data voltage to the pixels.

Abstract: A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Abstract: A display device includes: an insulation substrate; a plurality of gate lines on the insulation substrate and divided into a first group and a second group; a plurality of data lines insulated from and intersecting the gate lines; a gate driver which applies a gate-on voltage to the gate lines and operates in one of a first mode and a second mode; and a data driver which applies a data voltage to the data lines, where the first group and the second group of the gate lines are applied with the gate-on voltage when the gate driver is in the first mode, and where the first group of the gate lines is applied with the gate-on voltage and the second group of the gate lines is in an off state when the gate driver is in the second mode.

Abstract: The present invention relates to tricarbonyl technetium-99m or rhenium-188 labeled cyclic RGD derivatives, a preparation method thereof, and a pharmaceutical composition containing the derivative as an active ingredient for use in the diagnosis or treatment (radiotherapy) of angiogenesis-related diseases. The tricarbonyl technetium-99m or rhenium-188 labeled cyclic RGD derivatives of the present invention has a high subnanomolar affinity to integrin ?v?3 (also called as a vitronectin receptor) that is activated in an angiogenic action induced by a tumor, reflects a high tumor image of the tricatvonyl technetium-99m labeled cyclic RGD derivative after initial intake in an animal in which cancer cells are transplanted, and acts exclusively upon cancer cells having selectively activated integrin ?v?3 because of a substantially low intake into the liver and intestines, compared to existing known radioactive isotope labeled cyclic RGD derivatives.

Abstract: A gate driving circuit includes a plurality of stages outputting gate signals to a plurality of gate lines. Each of the stages includes a circuit transistor, a capacitor part, a first connecting electrode and a second connecting electrode. The circuit transistor outputs the gate signal to an output electrode in response to a control signal inputted to a control electrode. The capacitor part is disposed adjacent to the circuit transistor, and includes a first electrode, a second electrode disposed over the first electrode, a third electrode disposed over the second electrode and a fourth electrode disposed over the third electrode. The first connecting electrode electrically connects the control electrode to the first and third electrodes. The second connecting electrode electrically connects the output electrode to the second and fourth electrodes.

Abstract: A display apparatus includes a backlight assembly, a driving circuit part, and a display panel. The backlight assembly emits light. The driving circuit part receives an image signal, converts the image signal into image data, and generates a driving signal based on the image data. The display panel includes at least one pixel in which a plurality of sub-pixels is arranged in a two row by four column array, wherein the panel receives the light to display an image in response to the driving signal, wherein two sub-pixels of the sub-pixels arranged in a first row of the array each comprise a white color filter and two sub-pixels of the sub-pixels arranged in a second row of the array each comprise a white color filter.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: An amorphous anode active material, a preparation method of an electrode using the same, a secondary battery containing the same, and a hybrid capacitor are provided. The amorphous anode active material includes at least one of a metal oxide or a metal phosphate, and the metal oxide or the metal phosphate is amorphous. The metal oxide has the form of MOx (0<X?3). M is at least one of molybdenum (Mo), vanadium (V), scandium (Sc), titanium (Ti), chromium (Cr), yttrium (Y), zirconium (Zr), niobium (Nb) and tungsten (W). The metal phosphate has the form of AxBy(PO4) (0?x?2, 0<y?2). A is at least one of lithium (Li), sodium (Na) and potassium (K), and B is at least one of molybdenum (Mo), vanadium (V), scandium (Sc), titanium (Ti), chromium (Cr), yttrium (Y), zirconium (Zr), niobium (Nb) and tungsten (W).