Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: Disclosed is a pouch-type secondary battery having a sealing margin for improved durability, including a sealing area formed by melting sealing layers of an upper pouch film and a lower pouch film along edges of a pouch casing, characterized in that a sealing margin is greater than a movement distance of a sealing residue flowing out of the sealing area, the sealing margin being a distance measured from an intersection point of a first straight line and a second straight line to a boundary line of the sealing area, the first straight line extending horizontally from a surface of the sealing area, when viewed in cross section of the secondary battery, and the second straight line corresponding to a tangent line having an average gradient among possible tangent lines at each point on a cross-sectional slope line of the pouch casing adjacent to the sealing area.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A display apparatus includes a display panel including a plurality of pixel columns to display an image, wherein each of the pixel columns includes a plurality of pixels arranged in a first direction and sequentially turned-on in the first direction; a gate driver disposed on the display panel and including a plurality of stages connected to the pixels to sequentially apply a gate signal to the pixels, where at least two stages of the stages are disposed adjacent to each other in a second direction different from the first direction; and a data driver which applies a data voltage to the pixels.

Abstract: A display apparatus includes a backlight assembly, a driving circuit part, and a display panel. The backlight assembly emits light. The driving circuit part receives an image signal, converts the image signal into image data, and generates a driving signal based on the image data. The display panel includes at least one pixel in which a plurality of sub-pixels is arranged in a two row by four column array, wherein the panel receives the light to display an image in response to the driving signal, wherein two sub-pixels of the sub-pixels arranged in a first row of the array each comprise a white color filter and two sub-pixels of the sub-pixels arranged in a second row of the array each comprise a white color filter.

Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a semiconductor substrate doped with a first conductive type impurity through which a via hole passing from a first surface of the semiconductor substrate to a second surface thereof facing the first surface is formed, wherein the first surface is a light receiving surface, upper and lower emitter layers respectively formed on upper and lower surfaces of the semiconductor substrate and doped with a second conductive type impurity that is different from the first conductive type impurity, current collecting layers formed on sidewalls of the via hole and doped with a higher concentration of the first conductive type impurity than that of the semiconductor substrate, a contact electrode extending from the first surface of the semiconductor substrate to the second surface thereof so as to fill the via hole, and upper and lower electrodes respectively contacting the upper and lower emitter layers.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.

Abstract: A display device includes: an insulation substrate; a plurality of gate lines on the insulation substrate and divided into a first group and a second group; a plurality of data lines insulated from and intersecting the gate lines; a gate driver which applies a gate-on voltage to the gate lines and operates in one of a first mode and a second mode; and a data driver which applies a data voltage to the data lines, where the first group and the second group of the gate lines are applied with the gate-on voltage when the gate driver is in the first mode, and where the first group of the gate lines is applied with the gate-on voltage and the second group of the gate lines is in an off state when the gate driver is in the second mode.

Abstract: A novel alpha-1 antitrypsin variant, a method of preparing the same, and use thereof are provided. The alpha-1 antitrypsin variant has excellent stability in the body and maintains an inhibitory effect on elastase activities because the blood half-life (t1/2) and the area under blood drug concentration vs. time curve (AUC) are remarkably increased by adding an N-glycosylation site in animal cells through amino acid mutation between 1st and 25th positions of the N-terminus of alpha-1 antitrypsin. Therefore, the alpha-1 antitrypsin variant can be useful in preventing or treating alpha-1 antitrypsin deficiency.

Abstract: A display apparatus includes a backlight assembly, a driving circuit part, and a display panel. The backlight assembly emits light. The driving circuit part receives an image signal, converts the image signal into image data, and generates a driving signal based on the image data. The display panel includes at least one pixel in which a plurality of sub-pixels is arranged in a two row by four column array, wherein the panel receives the light to display an image in response to the driving signal, wherein two sub-pixels of the sub-pixels arranged in a first row of the array each comprise a white color filter and two sub-pixels of the sub-pixels arranged in a second row of the array each comprise a white color filter.

Abstract: A display device includes pixels, gate lines, and data lines on a substrate. The pixels include sub-pixels, and each sub-pixel includes a respective one of a plurality of first electrodes connected to one of the gate lines and one of the data lines. The first electrode of the sub-pixel at an n-th row and the first electrode of the sub-pixel at an (n+2)-th row in a same column are connected to different ones of the data lines. The sub-pixels in the n-th and (n+2)-th rows in the same column emit the same color of light.

Abstract: Disclosed is a pollution measurement apparatus which measures a pollutant concentration and a pollutant component in gas, and more particularly a pollution measurement apparatus for easily exchanging a sensor, which can facilely exchange only desired sensors when it is required to exchange part of multiple sensors for sensing pollution.

Abstract: A liquid crystal display includes a first gate line; a common voltage line separated from the first gate line; a data line insulated from and crossing the first gate line and the common voltage line; a first switching element connected to the first gate line and the data line; a second switching element connected to the first gate line and the data line; a first liquid crystal capacitor connected to the first switching element; a second liquid crystal capacitor connected to the second switching element; a third switching element connected to the first switching element; an assistance capacitor connected to the third switching element and the common voltage line; and a shielding electrode extending in the same direction as the first gate line and connected to the first switching element.

Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a dielectric film on a semiconductor substrate doped with a first conductive type impurity, exposing a high concentration doping region of a predetermined selective emitter by partially removing the dielectric film, and ion-implanting a second conductive type impurity into a front surface of the semiconductor substrate with the dielectric film formed thereon to form a high concentration doping layer in the semiconductor substrate to correspond to the high concentration doping region and to form a low concentration doping layer in the semiconductor substrate to correspond to a region in which the dielectric film is formed.

Abstract: A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A three-dimensional (3D) image display device includes data lines, gate lines crossing the data lines, sub-pixels arranged in areas between the data lines and the gate lines, a data driver that drives the data lines, a first gate driver that drives first gate lines from among the gate lines, a second gate driver that drives second gate lines from among the gate lines, and a timing controller that controls the data driver, the first gate driver, and the second gate drivers according to an image signal and a control signal. The second gate driver does not drive the second gate lines during a 3D display mode.