Abstract: Embodiments of this application relate to the field of power source control technologies, and disclose a control system and a charging and discharging control system. The control system includes a control circuit and an intermediate computer, where the control circuit includes a pressure sensor, a piezoelectric valve, and a controller; the pressure sensor is configured to collect pressure information; the controller is configured to receive the pressure information collected by the pressure sensor and transmit the pressure information to an intermediate computer; the intermediate computer is configured to transmit the pressure information to an upper computer, receive a preset pressure value generated by the upper computer based on the pressure information, and transmit the preset pressure value to the controller; and the controller is further configured to control the piezoelectric valve based on the preset pressure value.

Abstract: A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

Abstract: Disclosed is a compound as shown in formula (I) or a pharmaceutically acceptable salt, a stereoisomer, an isotope derivative or a prodrug thereof. The compound has an excellent activity as a cyclin-dependent kinase 9 (CDK9) inhibitor for treating hyperproliferative diseases. The experimental research on in vitro inhibition of cell proliferation and in vivo suppression of tumors shows that such compounds have a relatively strong inhibitory effect on MV4;11 cells and in vivo tumor models, and have a good selectivity and a low toxicity and few side effects, thereby possessing a good clinical value as novel anti-tumor drugs.

Abstract: The present disclosure provides a method and an apparatus for detecting a data path, and a storage medium, relates to the technical field of semiconductors, and is applied to a process of detecting a data path of a semiconductor integrated circuit. The method for detecting a data path includes: disconnecting, by a detection apparatus, a connection between a global data line and a local data line in the data path, writing test data into the global data line in the data path via the data path through a write port of the data path, reading, by the detection apparatus, target data of the global data line under a preset condition, and further detecting a defect of the data path according to the test data and the target data.

Abstract: A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit.

Abstract: A test method and a test system are provided. The method includes that: first initial data is written into the storage module; ECC module encodes and generates first check data corresponding to first initial data based on first initial data, and writes first check data into the storage module; second initial data is written into a same address of the storage module; second initial data and first check data in the storage module are read. ECC module encodes and generates second check data corresponding to second initial data based on second initial data, and checks and corrects second initial data based on the first check data and the second check data; first read data of the memory is read, and whether a function of ECC module is abnormal is determined based on the first read data, the first read data is checked and corrected second initial data.

Abstract: A radiosynthesis system is disclosed that leverages droplet microfluidic radiosynthesis and its inherent advantages including reduction of reagent consumption and the ability to achieve high molar activity even when using low starting radioactivity. The radiosynthesis system enables the parallel synthesis of radiolabeled compounds using droplet-sized reaction volumes. In some embodiments, a single heater is used to create multiple reaction or synthesis sites. In other embodiments, separate heaters are used to create independently-controlled heating conditions at the multiple reaction or synthesis sites. In one embodiment, a four-heater setup was developed that utilizes a multi-reaction microfluidic chip and was assessed for the suitability with high-throughput radiosynthesis optimization. Replicates of several radiochemical operations including the full synthesis of various PET tracers revealed the platform to have high repeatability (e.g., consistent fluorination efficiency).

Abstract: A method for interconversion between protocols, including the following steps: pre-establishing a publication/subscription list; when a packet published by a publisher is received, searching the publication/subscription list for a protocol type of the packet; extracting a packet data payload from the packet; determining whether a size of the packet data payload is less than a preset combination threshold; if yes, sending the packet data payload to a packet data payload queue of the publisher, and combining a packet data payload in the packet data payload queue when a size of the packet data payload queue reaches a preset transmission threshold or no new packet is received after a preset waiting duration; searching the publication/subscription list for all subscribers corresponding to the publisher; and performing protocol conversion on the packet one by one based on protocol types used by the corresponding subscribers, and sending protocol-converted packets to the corresponding subscribers.

Abstract: The clustered regularly interspaced short palindromic repeat (CRISPR) gene editing technique, based on the non-homologous end-joining (NHEJ) repair pathway, can efficiently generate gene knockouts of variably sizes. More precise genome editing, either the insertion or deletion of a desired fragment, can be done by combining the homology-directed-repair (HDR) pathway with CRISPR cleavage. HDR-mediated gene knock-in experiments are inefficient, with no reports of successful gene knock-in with DNA fragments larger than 4 kb. Targeted insertion of large DNA fragments (7.4 and 5.8 kb) into the genomes of mouse embryonic stem cells and zygotes, respectively, using the CRISPR/HDR technique without NHEJ inhibitors was performed and indicate that CRISPR/HDR without NHEJ inhibitors can result in highly efficient gene knock-in, equivalent to CRISPR/HDR with NHEJ inhibitors.

Abstract: A preparation method of the microcapsules for low-temperature well cementation to be used to control cement hydration heat includes: (S1) a shell material, and added into deionized water, then the resultant mixture being stirred in a thermostat water bath so as to completely dissolve it into a homogeneous and stable shell material solution; (S2) a core material and an emulsifier being put into a three-necked flask and stirred in a thermostat water bath so as to uniformly emulsify and disperse them, forming a stable oil-in-water core material emulsion, while adjusting the pH value of the emulsion with a pH adjuster; (S3) the three-necked flask containing the core material emulsion being transferred to a water bath, and then the shell material solution being dropwise added into it with stirring, after reacting, a solid-liquid mixture being poured out so as to naturally cool it to room temperature.

Abstract: A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.

Abstract: A memory includes a storage circuit, a first reading circuit, a second reading circuit, and a plurality of correcting circuits. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays. The sense amplifier arrays and the storage unit arrays are arranged alternately, and the sense amplifier arrays are configured to perform data reading and writing on the storage unit arrays. The first reading circuit is configured to compare a reference voltage signal with a signal on a first data line corresponding to the first reading circuit, and output a comparison result as read-out data. The second reading circuit is configured to compare the reference voltage signal with a signal on a first data line corresponding to the second reading circuit, and output a comparison result as read-out data.

Abstract: A PoE system includes a plurality of PoE devices and a hub that are coupled in a ring configuration through a plurality of network cables. The hub is coupled to two of the network cables, and provides electric power to at least one of the network cables that is coupled to the hub. Each of the PoE devices is coupled to two of the network cables, receives electric power from one of the two network cables, and supplies electric power to the other one of the two network cables. As a consequence, each of the PoE devices can be directly or indirectly powered by the hub.

Abstract: A graphical programming method, system and apparatus, a medium, a processor and a terminal are disclosed. The method includes displaying a first component including at least one port, in an interface; displaying a second component including at least one port, in an interface; in response to an operation of a user, enabling the second component to move, in the interface, towards the first component; and in response to a distance between a port of the second component and a port of the first component being less than a threshold distance, automatically forming a connecting line between the first component and the second component, two ends of the connecting line being respectively connected to a port of the first component and a port of the second component. As such, time consumption of interaction in graphical programming is reduced, programming time of a user is saved, and graphical programming efficiency is improved.

Abstract: Aspects of the subject disclosure may include, for example, automatically detecting a service issue of a telecommunication system that may impact a customer of a telecommunication service provider of the telecommunication system, predicting, by the processing system, a future customer care interaction by the customer as a result of the service issue, initiating a resolution action of the telecommunication system for the service issue before the customer contacts a customer care agent of the telecommunication service provider, wherein the initiating is responsive to the predicting the future customer care interaction and modifying a component of the telecommunication system to improve efficiency of operation of the telecommunication system by reducing a number of customer care contacts by customers of the telecommunication service provider. Other embodiments are disclosed.

Abstract: A PoE system includes a plurality of PoE devices and a hub that are coupled in a ring configuration through a plurality of network cables. The hub is coupled to two of the network cables, and provides electric power to at least one of the network cables that is coupled to the hub. Each of the PoE devices is coupled to two of the network cables, receives electric power from one of the two network cables, and supplies electric power to the other one of the two network cables. As a consequence, each of the PoE devices can be directly or indirectly powered by the hub.

Abstract: Disclosed in the present invention is an electric tool, comprising: a housing, comprising a first opening; working equipment; a power apparatus, at least partially located in the housing and driving the working equipment; a surrounding structure, at least partially surrounding the power apparatus, the surrounding structure defining a second opening; and a blocking structure located between the first opening and the second opening.

Abstract: A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

Abstract: A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

Abstract: A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit.