Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for delivering event content. One of the methods includes initiating, for one or more client devices, a subscription to a topic; receiving an event relevant to a topic; determining a number of channel servers that correspond to the topic, wherein each channel server is associated with one or more client devices; determining that the number of channel servers that correspond to the topic is greater than a threshold number of channel servers; writing the received event from the event processor to an event fan-out queue, in response to the determination that the number of channel servers that correspond to the topic is greater than the threshold number of channel servers; reading the received event from the event fan-out queue; and sending the received event to the one or more client devices associated with each respective channel server.

Abstract: Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A polar code encoding/decoding method in a communications system is provided, including: determining an information bit location set or a frozen bit location set of a polar code based on an interleaving operation or a corresponding de-interleaving operation; and encoding or decoding the polar code based on the determined information bit location set or frozen bit location set.

Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: Embodiments of the present invention disclose a polar code processing method and communications device. The method includes: obtaining, based on a target coded bit quantity M and preset first mapping relationship information, a first sequence number set of M uncoded bits that is corresponding to the target coded bit quantity M, the first mapping relationship information is used to indicate a one-to-one correspondence between a plurality of coded bit quantities and a plurality of uncoded bit sequence number sets, the M uncoded bits include K information bits, and M target coded bits are obtained after polar encoding is performed on the M uncoded bits; and selecting, from the first sequence number set of the M uncoded bits according to a preset first selection rule, K sequence numbers as a sequence number set of the K information bits.

Abstract: A system for additively manufacturing a build part. The system includes a build platform configured for disposition within a resin tank, and a light source configured to cure a layer of resin. The layer of resin is disposed adjacent to a pre-cure build surface of the build part. The system also includes a constrained surface located between the build platform and the light source and configured to form a boundary for the layer of resin disposed between the constrained surface and the pre-cure build surface. The constrained surface is configured to vibrate to reduce a separation force required to separate the constrained surface from a post-cure build surface of the build part. The system also includes a vibratory source configured to vibrate the constrained surface.

Abstract: A memory apparatus including a controller and at least one memory is provided. The controller provides a plurality of access commands and performs a command reordering method for the access commands. The command reordering method includes a rank level step, selecting at least one command having a rank address of a previous scheduling command from the access commands as at least one first candidate command; a bank level step, selecting at least one command having a different bank address compared to the previous scheduling command from the at least one first candidate command as at least one second candidate command; and selecting one command from the at least one second candidate command as a current scheduling command.

Abstract: Provided are a polymyxin derivative having a general formula I structure, and a preparation method and an application thereof. The method for preparing the polymyxin derivative comprises the following steps: (1) an Fmoc-AA-OP side chain free amino group of a protected basic amino acid reacting with a halogenated resin to obtain an Fmoc-AA-OP-resin; (2) the Fmoc-AA-OP-resin being coupled one by one to obtain a linear peptide-resin; (3) the linear peptide-resin selectively removing a protective group, and carrying out solid-phase cyclization to obtain a cyclic peptide-resin; (4) the cyclic peptide-resin undergoing acidic hydrolysis and ether precipitation to obtain a crude product of a cyclic polypeptide; (5) the crude product being purified and/or salt transferred and lyophilized to obtain a pure product of the cyclic polypeptide.

Abstract: A performance evaluation apparatus and a performance evaluation method are provided. The performance evaluation method includes: detecting multiple access commands of a memory controller for page miss so as to identify at least one page-missed command from the access commands; calculating an interval between the at least one page-missed command and a last conflict command to serve as a conflict command interval, wherein the last conflict command conflicts with the at least one page-missed command; and evaluating performance of the memory controller according to the conflict command interval.

Abstract: A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Abstract: A method includes selectively communicating each of a plurality of motor winding signals to a first node at an integrated circuit based on whether the corresponding motor winding is energized. A zero-crossing event at an unenergized motor winding signal is determined based the unenergized motor winding signal and based on a signal at the first node.

Abstract: A decoding method, an encoding method, a decoder and an encoder are disclosed. In an embodiment the decoding method includes receiving, at a receiver of a receiving side, signals from a transmitting side, the signals including a code word and decoding, at a decoder of the receiving side, the code word using a low density parity check (LDPC) code in which each n adjacent rows, n>1, in an extension part of a base parity check matrix (PCM) are orthogonal except for punctured information columns.

Abstract: Embodiments of the present invention disclose a polar code processing method and communications device. The method includes: obtaining, based on a target coded bit quantity M and preset first mapping relationship information, a first sequence number set of M uncoded bits that is corresponding to the target coded bit quantity M, the first mapping relationship information is used to indicate a one-to-one correspondence between a plurality of coded bit quantities and a plurality of uncoded bit sequence number sets, the M uncoded bits include K information bits, and M target coded bits are obtained after polar encoding is performed on the M uncoded bits; and selecting, from the first sequence number set of the M uncoded bits according to a preset first selection rule, K sequence numbers as a sequence number set of the K information bits.

Abstract: Methods and apparatuses for additive manufacturing using stereolithography (“SLA”) materials. The apparatus includes a platform for holding an assembly of SLA resin layers. The apparatus also includes a platform for holding an assembly of SLA resin layers. The apparatus also includes a first movable stage for depositing and curing a portion of the liquid SLA resin on the platform, forming a pattern of cured SLA resin. The apparatus also includes a second movable stage for depositing a low-viscosity non-SLA material in voids in the pattern of cured SLA resin. The apparatus also includes a cooler for cooling the low-viscosity non-SLA material below its freezing point until solidified.

Abstract: Various embodiments of a tire tread having at least one sipe comprising an S-shaped geometry are disclosed. In one embodiment, a tire is provided, comprising: a tread portion comprising tread block or tread rib; the tread block or the tread rib having at least one sipe, wherein the at least one sipe includes at least one convex portion and at least one concave portion forming an S-shaped geometry along at least a portion of a length of the sipe, wherein the S-shaped geometry along at least a portion of the length of the sipe has an amplitude (A1), and wherein the amplitude (A1) varies along a radial height of the sipe, and wherein the at least one sipe includes a first curvilinear portion and a second curvilinear portion oriented substantially radially within the sipe, and forming an S-shaped geometry along the radial height of the sipe.

Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Abstract: An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.

Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Abstract: A voltage regulator generates an output voltage that is a designed voltage level below the supply voltage. A reference voltage generator generates a reference voltage between ground and supply voltages. A voltage divider generates a feedback voltage between the supply and output voltages. An amplifier generates an amplifier output voltage based on a difference between the reference and feedback voltages. A buffer buffers the amplifier output voltage. A pass transistor receives the buffered voltage at its control node to sink an average load current appearing at the output node. A capacitor is connected between the supply and output voltages to provide a peak load current. A load-current-detecting transistor receives the buffered voltage at its control node to sense the load current. A compensation transistor compensates for leakage current. An internal load converts the sensed load current into a voltage control signal applied to the compensation transistor.