Abstract: A low voltage ripple charge pump with slew rate control includes a frequency divider, a clock generator, a current mirror, a switching circuit, a diode network, two capacitors, and a comparator. The frequency divider generates a clock signal from an oscillating signal. The clock generator generates first and second clock signals from the clock signal. The current mirror generates first and second current signals using a reference current. The switching circuit generates first and second voltage signals using the first and second clock signals and the first and second current signals. The comparator generates the oscillating signal based on the first and second voltage signals. The capacitors receive the voltage signals and are connected to the diode network for generating an output signal. The charge pump has low output voltage ripple with small filtering capacitance, which is achieved via slew rate control.

Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.

Abstract: A voltage regulator generates an output voltage that is a designed voltage level below the supply voltage. A reference voltage generator generates a reference voltage between ground and supply voltages. A voltage divider generates a feedback voltage between the supply and output voltages. An amplifier generates an amplifier output voltage based on a difference between the reference and feedback voltages. A buffer buffers the amplifier output voltage. A pass transistor receives the buffered voltage at its control node to sink an average load current appearing at the output node. A capacitor is connected between the supply and output voltages to provide a peak load current. A load-current-detecting transistor receives the buffered voltage at its control node to sense the load current. A compensation transistor compensates for leakage current. An internal load converts the sensed load current into a voltage control signal applied to the compensation transistor.

Abstract: A method includes selectively communicating each of a plurality of motor winding signals to a first node at an integrated circuit based on whether the corresponding motor winding is energized. A zero-crossing event at an unenergized motor winding signal is determined based the unenergized motor winding signal and based on a signal at the first node.

Abstract: An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.

Abstract: Various embodiments of a tire tread having at least one sipe comprising an S-shaped geometry are disclosed.

Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

Abstract: A method for providing information handling system (IHS) security includes providing a plurality of monitored IHSs coupled to a monitoring IHS through a network. A physical lock status is determined for each of the plurality of monitored IHSs using a respective lock sensor located in each monitored IHS. The physical lock status is received by the monitoring IHS for each of the plurality of monitored IHSs over the network. A security report that includes the physical lock status for each of the plurality of monitored IHSs is created. The security report is displayed on a display coupled to the monitoring IHS.

Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

Abstract: A method for providing information handling system (IHS) security includes providing a plurality of monitored IHSs coupled to a monitoring IHS through a network. A physical lock status is determined for each of the plurality of monitored IHSs using a respective lock sensor located in each monitored IHS. The physical lock status is received by the monitoring IHS for each of the plurality of monitored IHSs over the network. A security report that includes the physical lock status for each of the plurality of monitored IHSs is created. The security report is displayed on a display coupled to the monitoring IHS.

Abstract: A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.

Abstract: A tire having a section height, a maximum section width, an upper section above the maximum section width, and a lower section below the maximum section width is provided. The tire includes a circumferential tread, a pair of sidewalls, a pair of bead regions each having a bead core, and at least one carcass ply extending circumferentially about the tire from one bead region to the other. The at least one carcass ply is wound outwardly about at least one of the bead cores and extends toward the tread to form a turn-up portion that terminates at a turn-up end. The turn-up portion includes a concave segment that begins in the bead region and ends short of the turn-up end or at the turn-up end.

Abstract: A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.

Abstract: A tire, which has a maximum section width, an upper section above the maximum section width, and a lower section below the maximum section width, includes a circumferential tread, a pair of sidewalls, and a pair of bead portions. The tire further includes at least one carcass ply extending circumferentially about the tire from one bead portion to the other and first and second reinforcement plies extending circumferentially about the tire. The first and second reinforcement plies are provided between the at least one carcass ply and at least one of the sidewalls of the tire. The first and second reinforcement plies include lower ends that terminate in the lower section of the tire and upper ends that terminate in the upper section of the tire.

Abstract: The present invention provides a process for producing a treated or modified polymer, which process comprises the steps of: (I) providing a mixture comprising a liquid, an additive and a polymer, wherein the additive is dispersed in the liquid; and (II) heating the mixture obtained in step (I) to soften the surface of the polymer so that the additive attaches to the polymer.

Abstract: A stand set includes a first component with a tube-shaped element and two first legs, a second component with a ring-shaped element and two second legs, and a third component with two clamping parts and two openings. The tube-shaped element has two locating ears, each provided with a through hole. An object can be inserted into the tube-shaped element for being supported and the first legs are connected to the tube-shaped element. The ring-shaped element and the tube-shaped element telescope with each other, wherein the first legs are engaged in two notches of the ring-shaped element. The second legs connect the ring-shaped element, each provided with a protrusion being inserted into the corresponding through hole. When detaching the second component from the first component, the third component can be assembled with the second component by inserting the protrusions into the openings and clamping the second legs through the clamping parts.

Abstract: The disclosed subject matter provides low power layered LDPC decoders and related systems and methods. Exemplary embodiments of the disclosed subject matter can achieve significant reduction in memory access of the associated memories by bypassing the associated memories depending on the decoding algorithm (e.g., code rate) and the characteristic of the LDPC parity check matrix, thereby providing significant reductions power consumption of LDPC decoders. According to various embodiment, an optimal decoding order can be determined and scheduled to maximize the power reduction available by bypassing the associated memories. In addition, various algorithms are disclosed that determine optimal search orders under various constraints. According to the disclosed subject matter, particular embodiments can further reduce power consumption by employing the disclosed thresholding to further reduce memory access.

Abstract: A tire having a tread including first and second reinforcement plies disposed between at least one carcass ply and the tread and at least one of the sidewalls of the tire. A method for making a tire body ply is also described. The method includes delivering a first rubber coating, at least one insert, a body fabric, and a second rubber coating to a bite formed by at least two calendering rollers. The method further includes pressing the first rubber coating, the body fabric, the at least one insert, and the second rubber coating through the bite and then between the at least two calendering rollers to form a tire body ply. In another embodiment, the method includes spacing a first insert from a center of the tire body ply by a first distance and a second insert from the center of the tire body ply by a second distance.

Abstract: A tire, which has a maximum section width, an upper section above the maximum section width, and a lower section below the maximum section width, includes a tread extending circumferentially about the tire, a pair of sidewalls, a pair of bead portions, and at least one carcass ply extending circumferentially about the tire from one bead portion to the other. The tire further includes first and second reinforcement plies extending circumferentially about the tire and being disposed between the at least one carcass ply and the tread and at least one of the sidewalls of the tire. The first and second reinforcement plies have lower ends that terminate in the lower section of the tire.

Abstract: Low power Viterbi decoder techniques using Scarce State Transition (SST) and path pruning and related methods and systems are provided, which facilitate practical implementations that reduce the computational overhead and power consumption. In addition, the invention provides uneven-partitioned memory architectures for the survivor memory unit that advantageously exploits the characteristic of the maximum likelihood state probability distribution of the SST decoder facilitating further power reduction. The disclosed details enable various refinements and modifications according to decoder and system design considerations.