Patents by Inventor Jie Lin

Jie Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11840508
    Abstract: A catalyst system for olefin polymerization contains a main catalyst and a cocatalyst. The cocatalyst contains a twelve-membered ring compound represented by formula (M). The catalyst system is suitable for preparing polypropylene products having high stereoregularity and low ash, and can regulate the melt index of the products within a wide range by adjusting the amount of hydrogenation. It is also suitable for copolymerization systems to improve the copolymerization yield.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 12, 2023
    Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, BEIJING RESEARCH INSTITUTE OF CHEMICAL INDUSTRY, CHINA PETROLEUM & CHEMICAL CORPORATION
    Inventors: Jie Lin, Xiaofan Zhang, Ting Huang, Junhui Zhang, Junling Zhou, Zhufang Sun, Xianzhi Xia, Hui Zhao, Zifang Guo, Jin Zhao, Haitao Liu, Meiyan Fu, Jigui Zhang, Lin Qi, Lian Yan, Wei Cen, Yu Wang
  • Publication number: 20230395534
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao-Yi HUNG, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
  • Publication number: 20230391902
    Abstract: A magnesium-based solid, by means of determination based on a nitrogen adsorption method, has a multimodal pore distribution and a specific surface area of not less than 50 m2/g, and the pore size distribution of the solid is in a range of 1 nm to 300 nm. There is at least one peak within a pore size range of less than 10 nm, and there is at least another peak within a pore size range of not less than 10 nm. A catalyst is formed using the solid catalyst component is used for propylene polymerization.
    Type: Application
    Filed: October 15, 2021
    Publication date: December 7, 2023
    Inventors: Wei CEN, Junling ZHOU, Meiyan FU, Lian YAN, Zhan SHI, Xiaofan ZHANG, Xianzhi XIA, Zhengyang GUO, Jigui ZHANG, Jie LIN, Lin QI, Tianyi ZHANG, Junhui ZHANG, Hui ZHAO, Yu WANG, Ying WANG
  • Patent number: 11837598
    Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su, Ming-Fu Tsai, Jam-Wem Lee
  • Patent number: 11829546
    Abstract: The disclosure provides a border touch module, including a cover plate, a shielding layer, a first adhesive layer, a sensing electrode layer, a second adhesive layer, an opaque adhesive, and a backlight layer. The shielding layer is disposed below the cover plate. The first adhesive layer is disposed below the shielding layer. The sensing electrode layer is disposed below the first adhesive layer. The second adhesive layer is disposed below the sensing electrode layer. The opaque adhesive is disposed below the sensing electrode layer. The backlight layer is disposed below the opaque adhesive and is in the same plane as the second adhesive layer. The shielding layer has a backlight pattern, and the opaque adhesive has a light source hole. When the backlight layer is in the state of driving backlight, the light illuminates the backlight pattern of the shielding layer through the light source hole.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: November 28, 2023
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Ching-Kai Cho, Zhi Juan Lin, Ting-Chieh Chien, Wei Jie Lin, Hua Li Luo
  • Patent number: 11824281
    Abstract: An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: November 21, 2023
    Assignee: Micro Mobio Corporation
    Inventors: Guan-Wu Wang, Terng-Jie Lin, Yi-Hung Chen, Wen-Chung Liu, Weiping Wang
  • Patent number: 11817403
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
  • Patent number: 11807746
    Abstract: An impact-resistant polystyrene resin includes a continuous phase and a plurality of particles dispersed in the continuous phase. The average particle size of the particles is about 0.1 to 4.0 ?m, and the average distance between the particles is about 0.3 to 5.0 ?m. The impact-resistant polystyrene resin is made from a polystyrene composition including a polystyrene plastic, a styrene block copolymer, a processing aid, and an antioxidant.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: November 7, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuan-Yeh Huang, Jin-An Wu, Fu-Ming Chien, Yun-Chen Chang, Fan-Jie Lin
  • Publication number: 20230349192
    Abstract: A post cover that is formed from a plurality of separate pieces that are joined together by fastenings to make the cover where each piece is formed with a facing surface, the facing surface has a plurality of outer edges, and one or more peripheral flanges depend from one or more of the outer edges.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Jin-Jie Lin, Lydia A. Poulsen, Gregory S. Powell
  • Publication number: 20230344221
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20230338898
    Abstract: A paper-based micro-concentrator includes a bearing substrate, a fluid reservoir unit, a filter paper, an external electric field, an ion exchange membrane and a magnet. The fluid reservoir unit includes a first buffer solution tank and a second buffer solution tank, which are interval disposed on the bearing substrate. The filter paper is disposed on the bearing substrate, and two ends of the filter paper are respectively placed in the first buffer solution tank and the second buffer solution tank. The external electric field includes a cathode and an anode, which are respectively placed in the first buffer solution tank and the second buffer solution tank. The ion exchange membrane is disposed on the filter paper and close to the first buffer solution tank. The magnet is movably disposed under the bearing substrate.
    Type: Application
    Filed: July 19, 2022
    Publication date: October 26, 2023
    Applicant: National Chung Cheng University
    Inventors: Shau-Chun Wang, Lai-Kwan Chau, Jia-Jie Lin, Yuan-Yu Chen, Ya-Chuan Chen
  • Publication number: 20230324752
    Abstract: A display panel and a display apparatus are provided. The display panel includes an array substrate; a color film substrate; support pillars; pixel sub-units; and data lines. The support pillars include a primary support pillar that includes a first support pillar. The pixel sub-units are formed by crossing the scan lines and the data lines. The pixel sub-units each include a thin film transistor and a pixel electrode. The thin film transistor includes a gate, a source and a drain. The scan line is electrically connected to the gate. The data line is electrically connected to the source. The pixel electrode is electrically connected to the drain. The present disclosure can enhance supporting capacity of the display panel.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 12, 2023
    Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Jie LIN, Bingping LIU
  • Publication number: 20230324380
    Abstract: The present disclosure relates to the technical field of rapid detection of molecules, and specifically relates to a method for rapid fluorescent immunoassay (FIA) and chemiluminescent immunoassay (CLIA) based on electrokinetic acceleration. The method includes the following steps sequentially: S1. sample acceleration: applying an actuating signal to a chip on which a target molecule is dripped to obtain a chip binding to the target molecule, where the chip includes an electrode sheet and coating molecules is immobilized on the electrode sheet; and S2. secondary antibody acceleration: adding a secondary antibody for binding to the target molecule dropwise on the chip binding to the target molecule, and applying an actuating signal to the chip to obtain a chip binding to the secondary antibody. The method can effectively improve a rate of FIA and CLIA, and can speed up a detection process and meet the need for rapid point-of-care testing (POCT).
    Type: Application
    Filed: June 5, 2023
    Publication date: October 12, 2023
    Inventors: Xiaozhu Liu, Hai Xu, Yanmin Li, Jun Li, Yong Hu, Li Tong, Jie Lin, Zhidong Zhang, Lihua Yang, Liang Ma, Zheng Zeng, Linggao Zeng, Li Chen, Shengxi Wu, Shenghui Qin
  • Publication number: 20230326920
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: Yu-Hung YEH, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20230314896
    Abstract: An optical modulator includes a semiconductor substrate and an optical waveguide portion disposed on the semiconductor substrate. A signal contact that extends alongside the optical waveguide portion is disposed on the semiconductor substrate. A first ground line is disposed on the semiconductor substrate spaced away from the signal contact by a first spacing. A second ground line is disposed on the semiconductor substrate spaced away from the signal contact by a second spacing opposite the first ground line. The first spacing is different from the second spacing.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 5, 2023
    Inventors: Hamed PISHVAIBAZARGANI, Jie LIN, Masaki KATO
  • Publication number: 20230299088
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.
    Type: Application
    Filed: April 14, 2023
    Publication date: September 21, 2023
    Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
  • Publication number: 20230295285
    Abstract: Methods are provided for improved treatment of subjects with cancer anorexia-cachexia syndrome, comprising treatment with a combination of at least one anti-cancer agent and at least one GDF15 modulator. Methods are further provided for improved treatment of subjects with anti-cancer agents which induce cachexia, comprising further treating the subject with at least one GDF15 modulator.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 21, 2023
    Inventors: Jeno Gyuris, Lorena Lerner, Jie Lin
  • Publication number: 20230291628
    Abstract: This disclosure provides a carrier signal processing method and apparatus. In the method, clipping factors are determined based on scheduling information corresponding to at least two respective carrier signals in a first time unit, the clipping factors correspond to the at least two respective carrier signals in the first time unit and are used for clipping processing a combination signal of the at least two carrier signals in the first time unit. The at least two carrier signals and the clipping factors are sent to a radio unit for processing. In this solution, clipping factors are matched in real time with scheduling information respectively corresponding to a plurality of carrier signals in the first time unit, to improve clipping performance.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 14, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhengwei Gong, Yongchao Pan, Shiguo Guan, Jie Lin
  • Patent number: 11756953
    Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hao Chiang, Wun-Jie Lin, Jam-Wem Lee
  • Patent number: 11749673
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin