Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

Abstract: A power conversion system is disclosed, which comprises at least one conversion unit comprising a converter unit and a first power interface boards; at least one measurement unit comprising a measurement board and a second power interface boards; and a controller comprising a processing unit, and a third power interface board communicated with the processing unit, and the first power interface board and the second power interface board, wherein at least some of the communications between the third power interface board and the first and second power interface boards have independent bandwidths.

Abstract: The present disclosure relates to a method for controlling voltage balance of a serialized power switching device, comprising generating a reference voltage based on actual individual voltage of each switch of the serialized power switching device or setting a reference voltage based on supplied voltage to the serialized power switching device; determining an individual blocking voltage mismatch of at least one switch when existing a difference between the reference voltage and the actual individual voltage of at least one switch, wherein the individual voltage mismatch is based on the difference between the reference voltage and the actual individual voltage; calculating an individual delay mismatch for the at least one switch; and compensating the individual delay mismatch for the at least one switch. The present disclosure also relates to a system for controlling voltage balance of a serialized power switching device. The present disclosure also relates to a power switching device.

Abstract: A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.

Abstract: The invention provides novel biocompatible upconversion nanoparticle (UCNP) that comprises a core of cubic nanocrystals (e.g., comprising ?-Na Lna, Lnb Lnc F4) and an epitaxial shell (e.g., formed from CaF2; wherein Lnb is Yb), and related methods of preparation and uses thereof.

Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.

Abstract: A power conversion system includes one or more power conversion devices coupled to a grid connection. Each of the power conversion devices includes a power converter for converting a first multiphase current provided by the grid connection into a second current; a grid side filter coupled between the grid connection and an input of the power converter; a load side filter coupled to an output of the power converter; neutral points of the grid side filter and the load side filter connected together to form a first node; wherein the first node is not directly grounded.

Abstract: An integrated system for signal and power transmission with galvanic isolation is disclosed. The integrated system comprises an insulative layer having a primary side and a secondary side; a planar signal transformer and a planar power transformer for signal and power transmission between the primary and the secondary sides of the insulative layer respectively. The planar signal transformer comprises two signal coupling elements which are disposed on the primary and the secondary sides of the insulative layer respectively. The planar power transformer includes two power coupling elements which are disposed on the primary and the secondary sides of the insulative layer respectively. Each of the two signal coupling elements and the two power coupling elements is embedded in at least one layer of a multi-layer printed circuit board. The integrated system of the present disclosure has a compact structure and is suitable for automatic assembly and manufacturing.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

Abstract: The present disclosure relates to an integrated power semiconductor packaging apparatus and a power converter containing the integrated power semiconductor packaging apparatus. The integrated power semiconductor packaging apparatus comprises a plurality of power semiconductor devices and an electrically insulative substrate formed integrally. The electrically insulative substrate comprises a flat surface, at least one separation wall protruding from the flat surface and a flow channel inside the electrically insulative substrate. The at least one separation wall is configured to separate the flat surface into a plurality of flat areas, and each of the plurality of flat areas is configured to receive one of the plurality of power semiconductor devices. The flow channel is configured for allowing a coolant flowing through to remove heat from the plurality of power semiconductor devices.

Abstract: The present disclosure is directed to compositions and methods for treating osteoarthritis comprising increasing the expression of Dnmt3b and/or inhibiting aminobutyrate aminotransferase.

Abstract: A method for controlling a plurality of series connected switch modules each including at least two parallel connected electronic switches, the method includes the step of, in response to failure of any electronic switch of one or more switch modules, turning on any non-faulty electronic switch of one or more faulty switch modules when the electronic switches of other non-faculty switch modules are controlled to be turned on.

Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.

Abstract: A drive system includes a current sensor configured to generate a first current signal representative of a current flowing in one or more electrical devices electrically coupled together through a power supply bus, a power output bus, and a common ground. The drive system also includes a voltage sensor configured to generate a first voltage signal representative of a voltage with respect to the common ground in the one or more electrical devices. The drive system further includes a ground fault detection controller configured to determine a ground fault in the one or more electrical devices based on a change in at least one of the first current signal and the first voltage signal.

Abstract: The present disclosure relates to the alignment of moieties (e.g., nanoparticles and/or nanowires) into prescribed architectures on two- and/or three-dimensional substrates (e.g., nucleic acid nanostructures/crystals). The present disclosure also relates to a nucleic acid (e.g., DNA) lithography method that includes, in some embodiments, adsorbing a bare nucleic acid nanostructure onto a surface of a substrate, and etching the surface of the substrate containing the bare nucleic acid nanostructure, thereby producing a patterned substrate.

Abstract: The present disclosure relates to a snubber circuit which comprises a static snubber unit, connected in parallel with the switch, for balancing a static voltage sharing across a switch when the switch is in a state of turn-on or turn-off; and a dynamic snubber unit for balance a dynamic voltage sharing across the switch when the switch is in a process of turn-on or turn-off, comprising a dynamic voltage sharing capacitor connected in parallel with the switch and having a relationship between a capacitance and a voltage of the dynamic voltage sharing capacitor; and a controller for controlling the capacitance of the dynamic voltage sharing capacitor to be in a predetermined working area of capacitance rising while the voltage across the switch is increasing. The present disclosure also relates to a power semiconductor device.

Abstract: Disclosed in the present invention are a salt type and crystal type of 4H-pyrazolo[1, 5-alpha]benzimidazole compound and the preparation method and intermediate thereof.

Abstract: The present invention is directed to preservative-free solutions of bimatoprost and timolol for lowering intraocular pressure and treatment of glaucoma.

Abstract: A method for protecting a circuit is provided, wherein the circuit comprises a plurality of switch devices connected in series. The method comprises detecting a failure risk indicator of each switch device; determining whether each switch device has a failure risk based on the corresponding failure risk indicator; and making each of the switch device(s) having the failure risk in a constant on-state to eliminate the failure risk and prevent a failure of the switch device optionally if a number of the switch device(s) which have or had the failure risk is less than or equal to a preset value.

Abstract: The present invention is directed to preservative-free solutions of bimatoprost and timolol for lowering intraocular pressure and treatment of glaucoma.