Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.

Abstract: A method of forming a semiconductor device includes following steps. A semiconductor strip is formed extending above a semiconductor substrate. A shallow trench isolation (STI) region is formed over the semiconductor substrate. The semiconductor strip has a fin structure higher than a top surface of the STI region. The fin structure includes a channel portion and a source/drain (S/D) portion adjacent to the channel portion. A dummy gate stack is formed over the channel portion. The S/D portion is exposed by the dummy gate stack. A doping process is performed to a top of the S/D portion using first dopants. An epitaxy layer is formed around the top of the S/D portion. The epitaxy layer has second dopants. A conductivity type of the second dopants is different from a conductivity type of the first dopants. The dummy gate stack is replaced with a replacement gate stack.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: The invention relates to a multi-component composition for the manufacture of polyurethane/urea cementitious hybrid system, comprising at least one isocyanate component selected from the group consisting of monoisocyanate, polyisocyanate and NCO terminated prepolymer, at least one polyol, water, catalyst, at least one acidic additive, and hydraulic binder, wherein the acidic additive is at least one selected from the group consisting of Lewis acids, acid precursors and acidic buffers and is in an amount of 0.01 to 3 wt %, based on the total weight of the composition, to the preparation thereof, and to the use of the composition for the preparation of a flooring, waterproofing, screed, grouting, primer, wall paint, roofing or coating in construction applications.

Abstract: Provided is a new compound capable of effectively inhibiting ATX. The compound is represented by formula I, or the compound is a tautomer, a stereoisomer, a hydrate, a solvate, a salt, or a prodrug of the compound represented by formula I. In formula (I), R1 and R2 are independently selected from —H or —CH3, provided that: R1 and R2 are not —H at the same time or are not —CH3 at the same time.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: Provided is a compound. The compound is a compound represented by formula (A), or a tautomer, a stereoisomer, a hydrate, a solvate, a salt, or a prodrug of the compound represented by formula (A), where R is R1 and R2 are each independently selected from H, C1-C10 alkyl, C3-C10 cycloalkyl, C1-C10 alkoxyl, halogen, and —CN; and R3, R4, and R5 are each independently selected from C1-C10 alkyl, C3-C10 cycloalkyl, C1-C10 alkoxyl, halogen, and —CN, under a premise that: if R1 is —CH3, C1, or —CN, R2 is not H, and if R1 is H, R2 is not H, —CN, or —CH3.

Abstract: A chair backrest swing structure includes a chassis connecting seat, a backframe connecting seat and an elastic buffer and reset member. The chassis connecting seat is configured to be cooperatively mounted with a chassis. The backframe connecting seat is configured to be cooperatively mounted with a backframe. The backframe connecting seat is rotatably cooperated with the chassis connecting seat. The elastic buffer and reset member is configured to enable that the backframe connecting seat may implement buffer and reset when swung left and right on the chassis connecting seat.

Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.

Abstract: The invention provides novel biocompatible upconversion nanoparticle (UCNP) that comprises a core of cubic nanocrystals (e.g., comprising ?-Na Lna, Lnb Lnc F4) and an epitaxial shell (e.g., formed from CaF2; wherein Lnb is Yb), and related methods of preparation and uses thereof.

Abstract: A method of fabricating a trimmed fin includes: forming a preliminary fin including silicon and germanium protruding from a substrate, in which the preliminary fin has a first germanium concentration at a top surface of the preliminary fin and a second germanium concentration at a position beneath the top surface of the preliminary fin, and the first germanium concentration is less than the second germanium concentration; oxidizing an exposed surface of the preliminary fin to form a trimmed fin covered by an oxide layer; and removing the oxide layer to obtain the trimmed fin.

Abstract: Systems and methods for providing improved recommendations are disclosed. In some embodiments, the systems and methods may be used for vehicle recommendations. The system may include a server system configured to receive user historical vehicle preferences, user vehicle preferences, generate weighted feature data sets, and apply a similarity model to the generated weighted feature data set in order to determine a vehicle recommendation data set. A visual representation of the vehicle recommendation data set may then be provided to an interface associated with a user.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: The invention provides a method for cargo sorting, configured to control an end effector with a package placement platform to sort the cargo, and the method includes: moving the package placement platform to a package obtaining position and obtaining the cargo to be sorted that enters into the package placement platform; moving the package placement platform to a package storage location; and exerting a first force to push the cargo into a package storage unit. With the help of the package placement platform, the method of the invention can receive the packages of different types or different sizes or different material so as to sort and transport all kinds of packages.

Abstract: Disclosed embodiments provide systems and methods related to updating creatives generation models. The system may include at least one memory unit for storing instructions and at least one processor configured to execute the instructions to perform operations.

Abstract: A first aspect relates to a computer-implemented method for performing model compression. The method includes compressing a machine learning (ML) network model comprising a multiple layer structure to produce a compressed ML network model. The compressed ML network model maintains the multiple layer structure of the ML network model. The method generates a model file for the compressed ML network model. The model file includes the compressed ML network model and decoding information for enabling the ML network model to be decompressed and executed layer-by-layer.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of work function metal layers and an oxygen absorbing layer over a channel region of the semiconductor device, including forming a first work function metal layer over the channel region, forming an oxygen absorbing layer over the first work function metal layer, forming a second work function metal layer over the oxygen absorbing layer. A gate electrode metal layer is formed over the plurality of work function metal layers. The work function metal layers, oxygen absorbing layer, and gate electrode metal layer are made of different materials.

Abstract: There is provided a method of selectively patterning a device structure. A hollow shadow wall is formed on a substrate. The hollow shadow wall is formed of a base lying on a surface of the substrate, and one or more side walls connected to the base. The one or more side walls extend away from the surface of the substrate and around the base to define an internal cavity of the hollow shadow wall. A device structure supported by the substrate adjacent to the shadow wall is selectively patterned by using a deposition beam to selectively deposit a layer of deposition material on the device structure. The deposition beam has a non-zero angle of incidence relative to a normal to the surface of the substrate and an orientation in the plane of the substrate's surface, such that the shadow wall prevents deposition on a surface portion of the device structure within a shadow region defined by the shadow wall.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.