Patents by Inventor Jin Lu

Jin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170337274
    Abstract: The disclosed embodiments include computerized methods, systems, and devices, including computer programs encoded on a computer storage medium, for generating terms of a search query based on a user's spoken utterances, identifying multiple cross-platform messages based on the generated terms, and to generating, via a presentation device, a single interface that enables the user to interact with identified messages. Based on a spoken utterance, the disclosed embodiments may determine user-specified search terms and/or criteria, and based on the user-specified search terms and/or criteria, may obtain cross-platform message data that corresponds to the search query. The communications device may generate one or more interface elements that describe corresponding ones of the cross-platform messages, which may be presented within a unified graphical user interface or voice-user interface by a communications device.
    Type: Application
    Filed: May 17, 2016
    Publication date: November 23, 2017
    Inventors: Vinh Quoc Ly, Ahmet Onur Tekdas, Timo Mertens, Okan Kolak, Charles Randell Sievert, Christine Nguyen, Jin Lu
  • Publication number: 20170333334
    Abstract: Disclosed herein are coating compositions that may include at least one urethane (meth)acrylate oligomer having a molecular weight between about 2,000 g/mol and about 50,000 g/mol and at least one cycloaliphatic (meth)acrylate. The coating compositions may also optionally include at least one photo-initiator, adhesion promoter, pigment, dye and/or plasticizer. The coating compositions may be hardened, after application, by curing by exposure to radiant energy, by exposure to electron beam radiation, by exposure to heat, by exposure to chemicals and combinations thereof. Upon hardening, the coating composition typically has two phases, a soft phase which has a Tg between ?50° C. and 0° C. and a hard phase which has a Tg between 60° C. and 120° C. Methods of using the coating compositions are also described.
    Type: Application
    Filed: November 6, 2015
    Publication date: November 23, 2017
    Applicant: Arkema France
    Inventors: Jin Lu, Jingping WU, Xioxing DONG
  • Publication number: 20170316974
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 9800610
    Abstract: The disclosed computer-implemented method for defeating relay attacks may include (1) buffering, in a memory buffer, an encoded signal that has been sent to a remote device, (2) detecting, within a time interval of the encoded signal being sent, a second signal that corresponds to the encoded signal, (3) determining that a strength of the second signal is above a predetermined threshold, (4) determining, based on the strength of the second signal being above the predetermined threshold, that the second signal represents a relay attack, and (5) initiating a security action to defeat the relay attack. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 24, 2017
    Assignee: Symantec Corporation
    Inventor: Jin Lu
  • Patent number: 9754825
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Publication number: 20170162440
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Publication number: 20170148674
    Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: JIN LU, RITA J. KLEIN, DIEM THY N. TRAN, IRINA V. VASILYEVA, ZHIQIANG XIE
  • Publication number: 20170133585
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
  • Patent number: 9613864
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Publication number: 20170051096
    Abstract: An ethylenically unsaturated polyurethane, which is an oligomer or polymer, results from the reaction of A) an alcohol component comprising: A1) at least one hydroxylated polydiene oligomer or polymer which may optionally be alkoxylated and A2) at least one hydroxyl-functional ethylenically unsaturated compound, which is a monomer or oligomer, bearing at least one ethylenic unsaturation and B) an isocyanate component comprising at least one polyisocyanate with a functionality of at least 2, wherein the molar ratio OH/NCO is greater than 1 and wherein said polyurethane bears reactive free hydroxyl groups. Such ethylenically unsaturated polyurethanes are useful as components of curable compositions such as coatings or adhesives.
    Type: Application
    Filed: April 28, 2015
    Publication date: February 23, 2017
    Inventors: Jin Lu, Xiaoxing DONG
  • Publication number: 20170049684
    Abstract: A curable aqueous polyurethane dispersion is formed by reacting a polyol component with a polyisocyanate. The polyol component comprises a1) at least one non-ionic polyol, a2) at least one polyol bearing at least one ionic or potentially ionic group comprising an acid group or salt thereof and a3) at least one ethylenically unsaturated monoalcohol or polyol. The polyol component contains carbon atoms from renewable resources. A method for making the curable aqueous polyurethane dispersion, uses of the aqueous polyurethane dispersion, cured polyurethanes and nail polish formulations comprising aqueous polyurethane dispersions are also disclosed.
    Type: Application
    Filed: April 28, 2015
    Publication date: February 23, 2017
    Inventors: Jeffrey A. KLANG, Jin LU, Indu VAPPALA, Yuhong HE
  • Publication number: 20170049683
    Abstract: A nail polish composition, in particular nail polish formulation, is disclosed which is based on a specific solvent-free aqueous polyurethane polymer dispersion, which is derived from at least one isocyanate-terminated ethylenically unsaturated polyurethane pre-polymer in a reactive diluent, after a chain extension reaction with a chain extender bearing isocyanate-reactive groups. The polyurethane pre-polymer comprises at least one (meth)acrylate functional group and at least one isocyanate functional group.
    Type: Application
    Filed: April 28, 2015
    Publication date: February 23, 2017
    Inventors: Jeffrey A. KLANG, Jin LU, Indu VAPPALA
  • Patent number: 9577192
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: February 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
  • Patent number: 9572034
    Abstract: The disclosed computer-implemented method for securing wireless networks may include (1) receiving, at a physical access point, a request to improve the security of a wireless network that includes a client device and is serviced by an active virtual access point of the physical access point, (2) configuring a substitute virtual access point to service the wireless network by (a) configuring the substitute virtual access point to identify the wireless network using a substitute SSID and/or (b) secure the wireless network using a substitute passcode, (3) transmitting a notification that includes the substitute SSID and/or the substitute passcode to the client device that instructs the client device to connect to the wireless network via the substitute virtual access point, (4) connecting the client device to the substitute virtual access point, and (5) disabling the active virtual access point. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 14, 2017
    Assignee: Symantec Corporation
    Inventor: Jin Lu
  • Publication number: 20160362515
    Abstract: A curable aqueous polyurethane dispersion is formed by reacting a polyol a) component with a polyisocyanate b) in excess to form a polyurethane pre-polymer which is neutralized and dispersed before chain extending with a chain extender c) to form the final polyurethane polymer aqueous dispersion. The polyol a) component comprises a1) at least one non-ionic polyol, a 2) at least one polyol bearing at least one ionic or potentially ionic group comprising an acid group or salt thereof and a3) at least one ethylenically unsaturated monoalcohol or polyol. The polyol component contains carbon atoms from renewable resources. A method for making the curable aqueous polyurethane dispersion, uses of the aqueous polyurethane dispersion, cured polyurethanes are also disclosed.
    Type: Application
    Filed: February 25, 2015
    Publication date: December 15, 2016
    Inventors: Jeffrey A. KLANG, Jin LU, Indu VAPPALA, Yuhong HE
  • Publication number: 20160304742
    Abstract: A solvent-free aqueous curable polyurethane dispersion is derived from at least one isocyanate-terminated ethylenically unsaturated polyurethane pre-polymer in a reactive diluent. The polyurethane pre-polymer comprises at least one (meth)acrylate functional group and at least one isocyanate functional group. Methods for making a solvent-free aqueous polyurethane dispersion, curable compositions comprising the dispersion and resulting cured products are also disclosed.
    Type: Application
    Filed: November 21, 2014
    Publication date: October 20, 2016
    Inventors: Jeffrey A. Klang, Jin LU, Indu VAPPALA
  • Publication number: 20160293482
    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Hongqi Li, Gowrisankar Damarla, Robert J. Hanson, Jin Lu, Shyam Ramalingam
  • Patent number: 9430021
    Abstract: A battery management system/method implementing optimal dynamic battery charge/discharge cycling is disclosed. The system utilizes a power source control unit (PSCU) to selectively switch a power supply source to a battery charger that charges a battery servicing a portable computing device. The PSCU is controlled by a power monitor control unit (PMCU) that monitors the battery state and determines the optimal charge/discharge profile for the battery. Depending on the type and current condition of the battery as well as battery charge/discharge history, the PMCU monitors the historical, current, and/or anticipated demand activity of the battery to determine an optimal charge/discharge profile for the battery to enable maximum battery life under a wide variety of environmental and use profiles. Present invention methods control battery charge/discharge activity based on computing device historical/anticipated use characteristics, battery chemistry, and/or optimal battery lifecycle operation.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 30, 2016
    Assignee: ADVANERGY, INC.
    Inventors: Jin Lu, Todd Scott Kelly, Lee Cheung
  • Publication number: 20160247756
    Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
    Type: Application
    Filed: December 22, 2015
    Publication date: August 25, 2016
    Inventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan
  • Patent number: 9391001
    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Gowrisankar Damarla, Robert J. Hanson, Jin Lu, Shyam Ramalingam