Patents by Inventor Jin Lu

Jin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9335750
    Abstract: A security monitoring system/method implementing distributed Internet-based environmental monitoring and control is disclosed. The system utilizes a smart gateway power controller (SGPC) configured for new/retrofit installation into electrical power distribution networks to allow controlled connection of an AC power source to a customer load device under direction of local or remote Internet direction. The SGPC may also be configured with sensors to detect motion, audio, video, visual images, smoke, carbon monoxide, carbon dioxide, light/darkness, and other environmental data. The SGPC may be configured using a local web-based graphical user interface (GUI) to relay collected sensor information to a remote web browser hosted on a remote computing device. The GUI may incorporate a configuration/setup interface allowing mapping of sensor data to information associated with the sensor location and triggered security reports to occur based on collected sensor data.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: May 10, 2016
    Assignee: ADVANERGY, INC.
    Inventors: Jin Lu, Lee Cheung, Todd Scott Kelly
  • Publication number: 20160111372
    Abstract: Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Jin Lu, Hongqi Li, Kevin Torek, Thy Tran, Alex Schrinsky
  • Patent number: 9263459
    Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan
  • Patent number: 9252989
    Abstract: A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined NRZ condition for one or more of the noise prediction filters.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 2, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jin Lu, Shaohua Yang, Weijun Tan
  • Patent number: 9245698
    Abstract: A multi direction switch (100) includes a first cover (2), a second cover (3), a printed circuit board (PCB) (4) positioned between the first cover and the second cover, a pair of stacked, orthogonal electrode plates (5) positioned between the second cover and the PCB, a spring member (7) positioned between the first cover and the PCB, and a button (6) for actuating the electrode plates to move on the PCB. The second cover forms a protrusion (21), the button has a radial portion (611) and a wall portion (612) extending downwardly from the radial portion, and the spring member is positioned between the protrusion and the wall portion.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: January 26, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yusho Nakase, Jian-Jin Lu, Liang Sun
  • Patent number: 9206248
    Abstract: Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 8, 2015
    Assignee: Janssen Biotech, Inc.
    Inventors: Jill Carton, Jin Lu, Bernard Scallon, Linda Snyder
  • Publication number: 20150340282
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Publication number: 20150340247
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: Sony Corporation
    Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
  • Patent number: 9153451
    Abstract: A method of forming a planar surface for a semiconductor device structure. The method comprises forming a particle film comprising a plurality of discrete particles on a non-planar surface of a semiconductor device structure. The semiconductor device structure is subjected to at least one chemical-mechanical polishing process after forming the particle film on the non-planar surface of the semiconductor device structure. Methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrew Dennis Watson Carswell, Wayne Hai-Wei Huang, Siddartha Kondoju, Jin Lu, Suresh Ramakrishnan, Kozaburo Sakai, Sony Varghese, Andrey V. Zagrebelny
  • Patent number: 9147416
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: September 29, 2015
    Assignee: Avago Technologies General IP (Singapore) PTE. LTD.
    Inventors: Jeffrey P. Grundvig, Richard Rauschmayer, Yu Liao, Jin Lu, Edward J. D'Avignon
  • Publication number: 20150243322
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.
    Type: Application
    Filed: March 18, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: Jeffrey P. Grundvig, Richard Rauschmayer, Yu Liao, Jin Lu, Edward J. D'Avignon
  • Publication number: 20150243310
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
    Type: Application
    Filed: March 18, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: Jeffrey P. Grundvig, Richard Rauschmayer, Jin Lu
  • Publication number: 20150243583
    Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Gowrisankar Damarla, Shyam Ramalingam
  • Publication number: 20150227543
    Abstract: A method and apparatus for rapid replication of deduplicated file system data is described. The method may include initiating replication of a file from a source deduplication system to a destination deduplication system, and transferring deduplication metadata for each block of the file from the source deduplication system to the destination deduplication system. The method may also include transferring an identifier file from the source deduplication system to the destination deduplication system that includes a block number corresponding to a block of the file and a unique identifier value generated from the block of the file. The method may also include receiving a data request file from the destination deduplication system, and transferring the blocks of data identified in the data request file to complete replication of the file on the destination deduplication system.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 13, 2015
    Applicant: Atlantis Computing, Inc.
    Inventors: Chetan Venkatesh, Toby Jonathon Coleridge, Pu Paul Zhang, Vikram Auradkar, Seshan Parameswaran, Kartikeya Iyer, Qian Zhang, Jin Lu
  • Patent number: 9099442
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 9099132
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 4, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jeffrey P. Grundvig, Richard Rauschmayer, Jin Lu
  • Patent number: 9062305
    Abstract: Described and claimed herein are combinatorial synthetic Fab libraries displayed on a phage pIX protein. The libraries were built on scaffolds representing the most frequently used genes in human antibodies, which were diversified to mirror the variability of natural antibodies. After selection using a diverse panel of proteins, numerous specific and high-affinity Fabs were isolated. By a process called in-line maturation the affinity of some antibodies was improved up to one hundred-fold yielding low pM binders suitable for in vivo use. This work thus demonstrates the feasibility of displaying complex Fab libraries as pIX-fusion proteins for antibody discovery and lays the foundations for studies on the structure-function relationship of antibodies.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 23, 2015
    Assignee: Janssen Biotech, Inc.
    Inventors: Ping Tsui, Lei Shi, Jin Lu, John Wheeler, Brian Whitaker, Lionella Borozdina-Birch, Juan C. Almagro, Bernard Amegadzie, Mark Tornetta, Ramachandra Reddy, David M. Knight, Jinquan Luo, Raymond W. Sweet, Qiang Chen
  • Publication number: 20150147805
    Abstract: Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 28, 2015
    Inventors: Jill Carton, Jin Lu, Bernard Scallon, Linda Snyder
  • Patent number: 8980626
    Abstract: Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 17, 2015
    Assignee: Janssen Biotech, Inc.
    Inventors: Jill Carton, Jin Lu, Bernard Scallon, Linda Snyder
  • Publication number: 20150054164
    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Hongqi Li, Gowrisankar Damarla, Robert J. Hanson, Jin Lu, Shyam Ramalingam