Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

Abstract: A semiconductor device that includes a fin structure, and a channel epitaxial wrap around layer at each end of a channel portion of the fin structure. The semiconductor device also includes a gate structure including a gate dielectric having gate edge portions in direct contact with the channel epitaxial wrap around layer. A middle portion of the gate dielectric is in direct contact with a central channel portion of the fin structure between the two ends of the channel portion of the fin structure. Source and drain regions are present on opposing sides of the channel portion of the fin structure.

Abstract: An electronic device establishes a first Bluetooth connection to a first wireless earbud, where there is a wireless connection between the first wireless earbud and a second wireless earbud. The electronic device establishes a second Bluetooth connection to the second wireless earbud by using the first wireless earbud. The electronic device simultaneously maintains the first Bluetooth connection and the second Bluetooth connection.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: FET devices with bottom dielectric isolation and sidewall implants in the source and drain regions to prevent epitaxial growth below the bottom dielectric isolation are provided. In one aspect, a semiconductor FET device includes: a device stack(s) disposed on a substrate, wherein the device stack(s) includes active layers oriented vertically over a bottom dielectric isolation layer; STI regions embedded in the substrate at a base of the device stack(s), wherein a top surface of the STI regions is recessed below a top surface of the substrate exposing substrate sidewalls under the bottom dielectric isolation region, wherein the sidewalls of the substrate include implanted ions; source and drains on opposite sides of the active layers; and gates surrounding a portion of each of the active layers, wherein the gates are offset from the source and drains by inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: A point-to-multipoint data transmission method and device, the method including a left earbud and a right earbud of a true wireless stereo (TWS) headset separately performing pairing and service content negotiation with an electronic device. The left earbud receives left configuration information sent by the electronic device, to configure a left ISO channel, and the right earbud receives right configuration information sent by the electronic device, to configure a right ISO channel. The left earbud receives, based on the BLE-based audio profile, audio data that is sent by the electronic device through the left ISO channel, and the right earbud receives, based on the BLE-based audio profile, the audio data that is sent by the electronic device through the right ISO channel. The left earbud and the right earbud play the respectively received audio data based on a first timestamp.

Abstract: A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area.

Abstract: Semiconductor FET devices with bottom dielectric isolation and high-? first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: A semiconductor structure is provided that includes nanosheet containing devices having a bottom dielectric isolation structure and high quality source/drain (S/D) structures. In the present application, the bottom dielectric isolation structure is formed after the S/D structures to ensure high quality epitaxy for both long channel and short channel nanosheet containing devices. The bottom dielectric isolation structure of the present application has a first portion that is located beneath each nanosheet stack and a second portion that is located in a single diffusion break point trench.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

Abstract: A fork-sheet semiconductor device includes a first-type source/drain region on a substrate and a second-type source/drain region on the substrate and separated from the first-type source/drain region by an insulator pillar. The fork-sheet semiconductor device further includes a first metal portion and a second metal portion. The first metal portion completely covers a first upper surface and a first exposed sidewall the first-type source/drain region and the second metal portion completely covers a second upper surface and a second exposed sidewall the second-type source/drain region. The first and second metal portions are separated from one another by the insulator pillar. A first-type contact portion extends vertically from the first metal portion and an opposing second-type contact portion extends vertically from the second metal portion. A first upper interconnect structure contacts the first-type contact portion and a second upper interconnect structure contacts the second-type contact portion.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor. The fabrication operations include forming a nanosheet having a first nanosheet sidewall and a second nanosheet sidewall. The nanosheet is communicatively coupled to a source region at the first nanosheet sidewall. The nanosheet is communicatively coupled to a drain region at the second nanosheet sidewall. The nanosheet further includes a source-side nanosheet region that includes the first nanosheet sidewall. The nanosheet further includes a drain-side nanosheet region that includes the second nanosheet sidewall. Dopants are provided in the source-side nanosheet region using an in-situ doping process, wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region.

Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

Abstract: A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a stack of nanosheet layers, a first gate, and a first source/drain region. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor includes a plurality of nanowires, a second gate, and a second source/drain region. The first gate and the second gate are vertically aligned. The first source/drain region and the second source/drain region are vertically aligned.

Abstract: FET devices with bottom dielectric isolation and sidewall implants in the source and drain regions to prevent epitaxial growth below the bottom dielectric isolation are provided. In one aspect, a semiconductor FET device includes: a device stack(s) disposed on a substrate, wherein the device stack(s) includes active layers oriented vertically over a bottom dielectric isolation layer; STI regions embedded in the substrate at a base of the device stack(s), wherein a top surface of the STI regions is recessed below a top surface of the substrate exposing substrate sidewalls under the bottom dielectric isolation region, wherein the sidewalls of the substrate include implanted ions; source and drains on opposite sides of the active layers; and gates surrounding a portion of each of the active layers, wherein the gates are offset from the source and drains by inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor. The fabrication operations include forming a nanosheet having a first nanosheet sidewall and a second nanosheet sidewall. The nanosheet is communicatively coupled to a source region at the first nanosheet sidewall. The nanosheet is communicatively coupled to a drain region at the second nanosheet sidewall. The nanosheet further includes a source-side nanosheet region that includes the first nanosheet sidewall. The nanosheet further includes a drain-side nanosheet region that includes the second nanosheet sidewall. Dopants are provided in the source-side nanosheet region using an in-situ doping process, wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region.