Abstract: A semiconductor structure, and a method of making the same, includes an inner spacer located between channel nanosheets on a semiconductor substrate, a first portion of the inner spacer located on a first side of the semiconductor structure and a second portion of the inner spacer located on a second side opposing the first side, the first portion of the inner spacer on the first side including a protruding region extending outwards from a middle top surface of the first portion of the inner spacer, and a metal gate stack in direct contact with the inner spacer, the first portion of the inner spacer including the protruding region pinching off the metal gate stack for increasing a threshold voltage on the first side.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: A fork-sheet semiconductor device includes a first-type source/drain region on a substrate and a second-type source/drain region on the substrate and separated from the first-type source/drain region by an insulator pillar. The fork-sheet semiconductor device further includes a first metal portion and a second metal portion. The first metal portion completely covers a first upper surface and a first exposed sidewall the first-type source/drain region and the second metal portion completely covers a second upper surface and a second exposed sidewall the second-type source/drain region. The first and second metal portions are separated from one another by the insulator pillar. A first-type contact portion extends vertically from the first metal portion and an opposing second-type contact portion extends vertically from the second metal portion. A first upper interconnect structure contacts the first-type contact portion and a second upper interconnect structure contacts the second-type contact portion.

Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.

Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first diameter and having a first critical voltage. A second MTJ having a second diameter and having a second critical voltage, wherein the first diameter and the second diameter are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Abstract: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-? metal gate disposed over the first set of fins, and a second high-? metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

Abstract: This application provides an image dehazing method, apparatus, and device, and a computer storage medium. The method includes: in response to obtaining an image dehazing instruction, acquiring a first image and a second image corresponding to a target scene at the same moment. The method also includes calculating, based on a first pixel value of each pixel of the first image and a second pixel value of each pixel of the second image, haze density information of the each pixel; generating an image fusion factor of the each pixel according to the haze density information, the image fusion factor indicating a fusion degree between the first image and the second image; and fusing the first image and the second image according to the image fusion factor to obtain a dehazed image.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

Abstract: A method for retrieving an audio file includes: collecting an audio segment in real time; and for every two chronologically adjacent audio frames in a plurality of audio frames of the audio segment, acquiring a difference value between spectral centroids of a sub-band corresponding to the two audio frames, to obtain a plurality of difference values; and obtaining an audio fingerprint corresponding to the two audio frames based on the plurality of difference values. A quantity of the plurality of difference values equaling a quantity of sub-bands of one of the two audio frames. Each bit of the audio fingerprint being determined based on a comparison between a difference value corresponding to the bit and a preset difference value threshold. The method also includes retrieving, in an audio file library based on audio fingerprints of the plurality of audio frames, a target audio file matching the audio segment.

Abstract: A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material and a semiconductor channel material located on a substrate is provided. An additional dielectric spacer is formed on the dielectric spacer and within a gap. Dielectric spacer is removed. An epitaxial oxide layer is formed on the re-exposed recessed surfaces of the substrate. Germanium is formed on the epitaxial oxide layer. Sidewalls of each semiconductor channel material nanosheet are physically exposed. A source/drain is formed on a surface of the germanium. ILD material is formed above each source/drain and above an adjacent region. Portions of ILD material are removed such that sidewalls of the source/drain and germanium are exposed. The germanium is removed. A contact region is formed that wraps around the source/drain region.