Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.

Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.

Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.

Abstract: By directing an ion beam with a beam divergence ? on a process surface of a semiconductor substrate, parallel electrode trenches are formed in the semiconductor substrate. A center axis of the directed ion beam is tilted to a normal to the process surface at a tilt angle ?, wherein at least one of the tilt angle ? and the beam divergence ? is not equal to zero. The semiconductor substrate is moved along a direction parallel to the process surface during formation of the electrode trenches. A conductive electrode is formed in the electrode trenches, wherein first sidewalls of the electrode trenches are tilted to the normal by a first slope angle ?1 with ?1 =(?+?/2) and second sidewalls are tilted to the normal by a second slope angle ?2 with ?2 =(???/2).

Abstract: Transistor devices are described that include a first transistor and a second transistor coupled in parallel between a first terminal and a second terminal. The second transistor is based on a wide bandgap semiconductor material. The second transistor has a breakthrough voltage lower than a breakthrough voltage of the first transistor over a predetermined operating range. The predetermined operating range comprises at least an operating range for which the transistor device is specified.

Abstract: Transistor devices are provided. A transistor device includes a unipolar transistor coupled between a first terminal and a second terminal; and a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal. The bipolar transistor is configured to carry a majority of a current flowing through the transistor device when at least one of the current or a control voltage controlling the unipolar transistor and the bipolar transistor exceeds a predetermined threshold. The bipolar transistor is further configured to have a threshold voltage higher than a threshold voltage of the unipolar transistor, and a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V.

Abstract: A transistor is driven by a drive circuit that includes a logic unit and drive signal generator. The drive signal generator outputs a temporally variable drive voltage for driving the transistor, based on setpoint state information. A short-circuit information signal contains information about a possible short circuit of a load connected in series with the transistor load path. In response to this signal, the drive signal generator switches on the transistor at a first point in time by setting the transistor drive voltage to a value or a value range above a switch-on threshold value of the transistor, but limits the drive voltage to a maximum first switch-on voltage limit value. The drive signal generator maintains the drive voltage at maximally the first switch-on voltage limit value or sets the drive voltage to a value or a value range greater than or equal to a second switch-on voltage limit value.

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range.

Abstract: A semiconductor device includes a device doping region of an electrical device arrangement disposed in a semiconductor substrate. A portion of the device doping region has a vertical dimension of more than 500 nm and a doping concentration of greater than 1*1015 dopant atoms per cm3. The doping concentration of the portion of the device doping region varies by less than 20% from a maximum doping concentration in the device doping region.

Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.

Abstract: A drive circuit for driving a semiconductor switch includes an overload detector circuit connected to the semiconductor switch and designed to detect an overload state of the semiconductor switch. The drive circuit further includes a driver circuit connected to a control terminal of the semiconductor switch and designed to generate, upon detection of an overload state, a driver signal having a level such that the semiconductor switch is switched off or switch-on is prevented. The driver circuit is further designed to generate a driver signal for driving the semiconductor switch according to a control signal, wherein for switching on the transistor at a first instant a driver signal is generated at a first level and, if no overload state is detected up to a predefined time period having elapsed, the level of the driver signal is increased to a second level.

Abstract: A method of operating an IGBT is described. The IGBT has gate, emitter and collector terminals, and IGBT cells, switchable diode cells, and non-switchable diode cells integrated in a semiconductor substrate, wherein each of the IGBT cells and switchable diode cells includes an operable switchable channel region. The IGBT is operated in a reverse conductive mode in which the IGBT cells are in a non-conductive mode and the switchable diode cells and the non-switchable diode cells are in a bipolar mode. The IGBT is brought from the reverse conductive mode to a transit mode in which at least some of the non-switchable diode cells are still in the bipolar mode, the IGBT cells are in the non-conductive mode, and the switchable diode cells are in a unipolar mode, by applying a gate voltage having an absolute value larger than a gate threshold voltage to the gate terminal.

Abstract: A semiconductor device includes a semiconductor substrate having a body layer arranged between a front side and a drift layer, and forming a pn-junction with the drift layer. A front metallization is on the front side in Ohmic connection with the body layer, and a back metallization opposite is in Ohmic connection with the drift layer. An IGBT cell region of the device includes a plurality of gate electrodes in Ohmic connection with a gate metallization. Each gate electrode is electrically insulated from the semiconductor substrate by a respective gate dielectric extending through the body layer. A free-wheeling diode region of the device includes a plurality of field electrodes in Ohmic connection with the front metallization. Each field electrode is separated from the semiconductor substrate by a respective field dielectric extending through the body layer. Additional semiconductor device embodiments are described.

Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.

Abstract: A semiconductor device includes a semiconductor body and a rear side insertion structure. The semiconductor body has a first surface at a front side and a second surface parallel to the first surface at a rear side, an active area and an edge termination area separating the active area from an outer surface of the semiconductor body. The outer surface connects the first and second surfaces, and element structures in the active area are predominantly formed closer to the first surface than to the second surface. The rear side insertion structure extends from the second surface into the semiconductor body in the edge termination area.

Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range.

Abstract: Crystal lattice defects are generated in a horizontal surface portion of a semiconductor substrate and hydrogen-related donors are formed in the surface portion. Information is obtained about a cumulative dopant concentration of dopants, including the hydrogen-related donors, in the surface portion. Based on the information about the cumulative dopant concentration and a dissociation rate of the hydrogen-related donors, a main temperature profile is determined for dissociating a defined portion of the hydrogen-related donors. The semiconductor substrate is subjected to a main heat treatment applying the main temperature profile to obtain, in the surface portion, a final total dopant concentration deviating from a target dopant concentration by not more than 15%.