Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

Abstract: An electric assembly includes a bipolar switching device and a transistor circuit. The transistor circuit is electrically connected in parallel with the bipolar switching device and includes a normally-on wide bandgap transistor.

Abstract: An electric assembly includes a reverse conducting switching device and a rectifying device. The reverse conducting switching device includes transistor cells for desaturation configured to be, under reverse bias, turned on in a desaturation mode and to be turned off in a saturation mode. The rectifying device is electrically connected anti-parallel to the switching device. In a range of a diode forward current from half of a maximum rating diode current of the switching device to the maximum rating diode current, a diode I/V characteristic of the rectifying device shows a voltage drop across the rectifying device higher than a saturation I/V characteristic of the switching device with the transistor cells for desaturation turned off and lower than a desaturation I/V characteristic of the switching device with the transistor cells for desaturation turned on.

Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.

Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.

Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.

Abstract: A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device.

Abstract: A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.

Abstract: An apparatus and a method for implanting ions are disclosed. In an embodiment, the apparatus includes a receptacle configured to support the wafer, a source of dopants configured to selectively provide dopants to an implantation region of the wafer and a source of radiation configured to selectively irradiate the implantation region.

Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone.

Abstract: A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.

Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

Abstract: A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.

Abstract: A method of forming a semiconductor device includes irradiating a semiconductor body with particles. Dopant ions are implanted into the semiconductor body such that the dopant ions are configured to be activated as donors or acceptors. Thereafter, the semiconductor body is processed thermally.