Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

Abstract: A method for controlling a first switch and a second switch is suggested, wherein each switch is an RC-IGBT and wherein both switches are arranged as a half-bridge circuit. The method includes: controlling the first switch in an IGBT-mode; controlling the second switch such that it becomes desaturated when being in a DIODE-mode; wherein controlling the second switch starts before and lasts at least as long as the first switch changes its IGBT-mode from blocking state to conducting state.

Abstract: In accordance with one component, a power field effect transistor is proposed, including a substrate, a channel, a gate electrode, and a gate insulator. The gate insulator is arranged at least partly between the gate electrode and the channel and includes a material having a hysteresis with respect to its polarization, such that a switching state of the transistor produced by a voltage applied to the gate electrode is maintained after the voltage has been switched off. Furthermore, a half-bridge circuit is proposed, including a high-side transistor in accordance with the construction according to the disclosure, and a low-side transistor, and also methods and circuits for driving.

Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

Abstract: A semiconductor device includes a semiconductor body and a rear side insertion structure. The semiconductor body has a first surface at a front side and a second surface parallel to the first surface at a rear side, an active area and an edge termination area separating the active area from an outer surface of the semiconductor body. The outer surface connects the first and second surfaces, and element structures in the active area are predominantly formed closer to the first surface than to the second surface. The rear side insertion structure extends from the second surface into the semiconductor body in the edge termination area.

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

Abstract: A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.

Abstract: A semiconductor device includes a pn junction between a drift zone and a charge-carrier transfer region in a semiconductor body. An access channel provides a permanent charge carrier path connecting the drift zone with a recombination region through a separation region between the drift zone and the recombination region. The access channel adjusts a plasma density in the drift zone and the recombination region.

Abstract: A power device includes an active area having at least two switchable regions with different threshold voltages.

Abstract: A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm?3 at a first distance to the first surface and does not fall below 1E14 cm?3 over at least 60% of an interval between the first surface and the first distance.

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Abstract: A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.

Abstract: A semiconductor mesa is formed in a semiconductor layer between a first cell trench structure and a second cell trench structure extending from a first surface into the semiconductor layer. An opening is formed in a capping layer formed on the first surface, wherein the opening exposes at least a portion of the semiconductor mesa. Through the opening impurities of a first conductivity type are introduced into the exposed portion of the semiconductor mesa. A recess defined by the opening is formed.

Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.

Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

Abstract: A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs. A second doped region with a conductivity type opposite to the first doped region is formed based on the crystal lattice vacancies and hydrogen atoms.

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract: A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.

Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.

Abstract: A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.