Patents by Inventor John A. Trezza

John A. Trezza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100320365
    Abstract: In one aspect, the present invention provides photodetectors and components thereof having multi-spectral sensing capabilities. In some embodiments, photodetectors of the present invention provide a first photosensitive element comprising at least one accessway extending through the element and an electrical connection at least partially disposed in the accessway, the electrical connection accessible for receiving a second photosensitive element.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Inventors: John Trezza, Martin Ettenberg
  • Patent number: 7851348
    Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: December 14, 2010
    Inventors: Abhay Misra, John Trezza
  • Patent number: 7850060
    Abstract: A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions having been selected such that heating to a first temperature will cause a change in at least one of the at least two compositions such that the change will result in a new composition having a new composition melting point of a second temperature, greater than the first temperature and the melting point of at least a first of the at least two compositions, and heating the pair of contacts and the at least two compositions to the first temperature.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: December 14, 2010
    Inventor: John Trezza
  • Patent number: 7847412
    Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: December 7, 2010
    Inventor: John Trezza
  • Publication number: 20100304565
    Abstract: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
    Type: Application
    Filed: July 29, 2010
    Publication date: December 2, 2010
    Inventor: John Trezza
  • Patent number: 7838997
    Abstract: A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: November 23, 2010
    Inventor: John Trezza
  • Patent number: 7831151
    Abstract: An optical module has multiple optical devices. At least two of the multiple optical devices are a group. Each of the optical devices in the group are individually selectable relative to the others. The optical module also has a controller, coupled to the devices such that the controller can select which of the devices in the group will be active at a given time. A communications network has a first transmitter having a number of usable channels, a first receiver, and optical fibers connecting the first transmitter to the first receiver. The first transmitter has multiple lasers, at least some being selectable as either active or backup lasers. The multiple lasers are controllable such that, if a specific channel is in use by an active laser and a laser failure occurs for that channel, a redundant laser can be substituted for the active laser and, after the substitution, the specific channel can be used using the redundant laser.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: November 9, 2010
    Inventor: John Trezza
  • Publication number: 20100261297
    Abstract: A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Inventor: John Trezza
  • Patent number: 7808111
    Abstract: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: October 5, 2010
    Inventor: John Trezza
  • Patent number: 7803693
    Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 28, 2010
    Inventor: John Trezza
  • Publication number: 20100219503
    Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventor: John Trezza
  • Patent number: 7785931
    Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: August 31, 2010
    Inventor: John Trezza
  • Patent number: 7785987
    Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: August 31, 2010
    Inventor: John Trezza
  • Patent number: 7786592
    Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: August 31, 2010
    Inventor: John Trezza
  • Patent number: 7781886
    Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: August 24, 2010
    Inventors: John Trezza, John Callahan, Gregory Dudoff
  • Publication number: 20100197134
    Abstract: An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another.
    Type: Application
    Filed: April 16, 2010
    Publication date: August 5, 2010
    Inventor: John Trezza
  • Patent number: 7767493
    Abstract: A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of the second chip being a material that is malleable, bringing the aligned electrically conductive contact of the first chip into contact with the corresponding electrically conductive contact on the second chip, elevating the contact of the chips to a temperature that is below a liquidus temperature for both the rigid material and the material that is malleable while applying pressure to the chips so as to cause the rigid material to penetrate the malleable material and form an electrically conductive connection, and, following the forming of the electrically conductive connection, cooling the contacts to an ambient temperature.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: August 3, 2010
    Inventors: John Trezza, John Callahan, Gregory Dudoff
  • Publication number: 20100176844
    Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 15, 2010
    Inventors: Theodore J. (Ted) Wyman, John Trezza
  • Patent number: 7748116
    Abstract: A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: July 6, 2010
    Inventor: John Trezza
  • Publication number: 20100148343
    Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.
    Type: Application
    Filed: February 23, 2010
    Publication date: June 17, 2010
    Inventor: John Trezza