Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.

Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.

Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.

Abstract: A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.

Abstract: A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.

Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Abstract: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium.

Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.

Abstract: A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed.

Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.

Abstract: A device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces.

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract: A method of forming an electrical connection from a first chip, having a contact pad exposed through an opening in cover glass on the chip, to a second chip having a first side and a second side and involves attaching the second chip to the first chip, etching an annular via having an inner and outer perimeter, the inner perimeter corresponding to an outer perimeter of the contact pad, the annular via extending into and through the second chip and down to the cover glass such that the annular via's inner perimeter substantially corresponds to the contact pad's outer perimeter, filling the annular via with an insulator, removing semiconductor material of the second chip within the inner perimeter of the insulator to create a void extending from the second side to the contact pad, and filling at least some of the void with a conductive material.

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract: A system has a first chip having first semiconductor devices and first electrical connections, a second chip having second semiconductor devices and second electrical connections, and a third chip having third semiconductor devices and third electrical connections, the third chip being stacked on top of and physically spanning at least a portion of each of the first and second chips and being connected to the first and second chips.

Abstract: A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench in the portion, forming an island of semiconductor material within the annular trench, filling the annular trench with an electrically insulating material, removing at least some of the island of semiconductor material to create an exposed inner surface, metalizing at least a portion of the exposed inner surface with a material, and thinning an outer surface side of the substrate until at least the material from the metalizing is exposed on the outer surface side of the substrate.

Abstract: A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10 ?m and a depth of greater than about 50 ?m, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal.

Abstract: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium.