Abstract: Composite IC die structures comprising a first IC die that has a first region directly bonded to a second IC die across a hybrid-bond interface and a topographic feature extending from a second region of the first IC die. In some examples, a hybrid bond interface is fabricated prior to forming a topographic IC die feature. In other examples, a hybrid bond interface is fabricated after forming a topographic IC die feature. A PIC die comprising a planar optical waveguide further includes an optical coupler protruding from a region of the die. In another region of the PIC die metallization features are embedded with a dielectric material suitable for forming a hybrid bond with a surface of an EIC die. Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.

Abstract: Hybrid III-V silicon device structures including a silicon optical waveguide of a first width, a III-V semiconductor mesa of a second width and a current channel of a third width that is smaller than the second width. The third width may be only slightly larger than the first width to narrowly confine electrical current directly over the optical waveguide while the second width is significantly larger than the first width to efficiently transport heat away from the optical gain medium. The current channel has low electrical resistivity and one or more material layers within the mesa are converted to a compound comprising aluminum (Al) and oxygen (O) having higher electrical resistivity. A mesa may be fabricated from a III-V material stack comprising one or more Al-rich layers, which are preferentially oxidized to form resistive aluminum oxide regions that laterally encroach a center of the mesa where current is confined.

Abstract: Described herein are IC devices that include hybrid lasers formed with a bonding layer. Hybrid lasers include an active light-emitting region coupled to a waveguide. In a hybrid laser, the waveguide and the light-emitting regions are formed separately from different materials, e.g., the waveguide is a single-crystal silicon, and the light-emitting region includes III-V semiconductors. An amorphous group IV material, such as silicon or germanium, is advantageously used to bond the light-emitting region to the waveguide.

Abstract: Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one optical signal source, an emitting lens disposed on the PIC to steer light emitted by the at least one optical signal source in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a curved surface in a shape of a quarter cylinder that is configured to steer light emitted from the emitting lens in a direction substantially orthogonal to the first surface of the PIC.

Abstract: A method may include: forming a base layer on a substrate; forming a waveguide assembly on the base layer, where the waveguide assembly is surrounded by a cladding layer; forming a trench opening through the cladding layer and the base layer; forming an undercut void by etching the substrate through the trench opening, where the undercut void extends under the waveguide assembly and the base layer; and filling the trench opening with a filler to seal off the undercut void. Other embodiments are described and claimed.

Abstract: Silicon photonic (SiPh) integrated circuit (PIC) comprising an optical waveguide heater element is thermally isolated by one or more voids within a dielectric material that is over the heater element. A void over a heater element may be formed by patterning a sacrificial material feature that is then embedded within the dielectric material. The sacrificial material is removed through an opening in the dielectric material and the opening is then occluded to define a void that may be retained as a permanent feature having a low thermal conductivity. The void over the heater element may, along with one of more voids adjacent to the heater element and/or below an optical waveguide, may enhance thermal isolation of a heater element, enhancing its power efficiency.

Abstract: A silicon photonic (SiPh) integrated circuit on a substrate comprising a buried insulator layer of varying thickness between an optical waveguide and an underlying silicon layer. The insulator layer has a first thickness under a first length of the waveguide and a second, greater, thickness under a second length of the waveguide. Buried insulator layer thickness may be thinner where an optical mode is to be more confined during operation of the SiPh IC, and buried insulator layer thickness may be greater within localized regions where optical mode is to expand during operation of the SiPh IC. Accordingly, a transfer of optical energy to an underlying silicon layer of the substrate may be curtailed within one substrate region without impeding the transfer of thermal energy to the underlying silicon layer within another substrate region.

Abstract: A device comprising a silicon substrate and a waveguide on the silicon substrate. A groove is in the substrate, the groove having a sloped rear wall adjacent to the waveguide. A trench is in the substrate, the trench along a second direction generally orthogonal to the first direction across the sloped rear wall, the trench having a vertical wall at an intersection with the sloped rear wall. An optical fiber in the groove with one end of the optical fiber abutting the vertical wall.

Abstract: Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

Abstract: Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

Abstract: Embodiments may relate to a wavelength-division multiplexing (WDM) transceiver that has a silicon waveguide layer coupled with a silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may include a tapered portion that is coupled with the silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may be coupled with a first oxide layer with a first z-height, and the silicon nitride waveguide layer may be coupled with a second oxide layer with a second z-height that is greater than the first z-height. Other embodiments may be described or claimed.