Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for MEMS sensing device configured to determine inertial change applied to the device. In one instance, the device may comprise a laser arrangement configured to generate a light beam, and a waveguide configured to split the light beam into two portions. The waveguide may include two arms through which the respective portions of the light beam may respectively pass, and disposed substantially parallel with each other and joined together around their respective ends to recombine the portions into a light beam. One of the arms may be deformable. A deformation of the arm may result in a change of an optical path length of a portion of the light beam traveling through the arm, causing a detectable change in light intensity of the recombined light beam outputted by the waveguide. Other embodiments may be described and/or claimed.

Abstract: A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a MEMS device configured to determine inertial change applied to the device. In one instance, the device may comprise a laser arrangement configured to generate a light beam having a resonant wavelength, a waveguide configured to receive and output the light beam, and an optical resonator comprising a deformable closed loop and optically coupled to the waveguide to receive a portion of the light beam. A deformation of the optical resonator may result in a change of an optical path length of a portion of the light beam traveling through the optical resonator, causing a change in the resonant wavelength of the light beam outputted by the waveguide. Other embodiments may be described and/or claimed.

Abstract: A solid state photonics circuit having a liquid crystal (LC) layer for beam steering. The LC layer can provide tuning of an array of waveguides by controlling the application of voltage to the liquid crystal. The application of voltage to the liquid crystal can be controlled to perform beam steering with the light signal based on different tuning in each of the waveguides of the array. The waveguides are disposed in a substrate having an oxide or other insulating layer with an opening. The opening in the oxide layer exposes a portion of a path of the array of waveguides. The waveguides are exposed to the liquid crystal through the oxide opening, which allows the voltage changes to the liquid crystal to tune the optical signals in the waveguides.

Abstract: Techniques and mechanisms for a monolithic photonic integrated circuit (PIC) to provide spectrometry functionality. In an embodiment, the PIC comprises a photonic device, a first waveguide and a second waveguide, wherein one of the first waveguide and the second waveguide includes a released portion which is free to move relative to a substrate of the PIC. During a metering cycle to evaluate a material under test, control logic operates an actuator to successively configure a plurality of positions of the released portion relative to the photonic device. In another embodiment, light from the first waveguide is variously diffracted by a grating of the photonic device during the metering cycle, where portions of the light are directed into the second waveguide. Different wavelengths of light diffracted into the second waveguide may be successively detected, for different positions of the released portion, to determine spectrometric measurements over a range of wavelength.

Abstract: Inverted 45° semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45° semiconductor mirror functions to couple light between a plane in the PIC chip defined by thin film layers and a direction normal to a top surface of the PIC chip where it may be generated or collected by an off-chip component, such as a wire terminal. In an exemplary embodiment, a (110) plane of a cubic crystalline semiconductor may provide a 45° facet inverted relative to a (100) surface of the semiconductor from which light is to be emitted. In further embodiments, a (110) plane may be exposed by undercutting a device layer of a semiconductor on insulator (SOI) substrate. Alternatively, a pre-etched substrate surface may be bonded to a handling wafer, thinned, and then utilized for PIC waveguide formation.

Abstract: Embodiments of the present disclosure are directed towards a micro-electromechanical system (MEMS) sensing device, including a laser arrangement configured to generate a light beam, a first waveguide configured to receive and output a first portion of the light beam, and a second waveguide having a section that is evanescently coupled to the first waveguide and configured to receive and output a second portion of the light beam. The section of the second waveguide is configured to be movable substantially parallel to the first waveguide, wherein a movement of the section of the second waveguide may be caused by an inertial change applied to the sensing device. The movement of the section may cause a detectable change in light intensity between the first and second portions of the light beam. Based on the detected change, the inertial change may be determined. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe semiconductor substrate techniques and configurations for an optical receiver. In one embodiment, a system includes a semiconductor substrate having one or more optical alignment features formed in a surface of the semiconductor substrate and an optical receiver assembly coupled with the semiconductor substrate, the optical receiver assembly including a photodetector device coupled with the surface of the semiconductor substrate, wherein the one or more optical alignment features facilitate precise optical alignment between a lens assembly and the photodetector device when the lens assembly is coupled with the semiconductor substrate using the one or more optical alignment features. Other embodiments may be described and/or claimed.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods may include forming a photomask on a (110) silicon wafer substrate, wherein the photomask comprises a periodic array of parallelogram openings, and then performing a timed wet etch on the (110) silicon wafer substrate to form a diffraction grating structure that is etched into the (110) silicon wafer substrate.

Abstract: Embodiments of the invention include systems and methods related to respiratory support delivered to infants using limited-leak cannulas. In an embodiment, the invention includes a method of providing respiratory support to an infant. The method can include attaching a limited-leak cannula having prongs to an inspiratory port of a ventilator with connection tubing. The method can include selecting an operations mode on the ventilator that is specific for unidirectional flow limited-leak cannula use. The method can include initiating a calibration procedure with the prongs of the cannula freely exposed. The calibration procedure can include measuring the flow rate of gas through the connection tubing at a set pressure. The method can include setting monitoring parameters on the ventilator, initiating respiratory support by inserting the cannula prongs into the nares of the infant, and continuously monitoring the flow rate of gas through the limited-leak cannula. Other embodiments are also included herein.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for MEMS sensing device configured to determine inertial change applied to the device. In one instance, the device may comprise a laser arrangement configured to generate a light beam, and a waveguide configured to split the light beam into two portions. The waveguide may include two arms through which the respective portions of the light beam may respectively pass, and disposed substantially parallel with each other and joined together around their respective ends to recombine the portions into a light beam. One of the arms may be deformable. A deformation of the arm may result in a change of an optical path length of a portion of the light beam traveling through the arm, causing a detectable change in light intensity of the recombined light beam outputted by the waveguide. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a MEMS device configured to determine inertial change applied to the device. In one instance, the device may comprise a laser arrangement configured to generate a light beam having a resonant wavelength, a waveguide configured to receive and output the light beam, and an optical resonator comprising a deformable closed loop and optically coupled to the waveguide to receive a portion of the light beam. A deformation of the optical resonator may result in a change of an optical path length of a portion of the light beam traveling through the optical resonator, causing a change in the resonant wavelength of the light beam outputted by the waveguide. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the invention use crystallographic etching of SOI wafers with a (110)-oriented epi layer to form both the vertical input facet and the re-entrant mirror. Proposed layout design combined with proposed orientation of the epi enables both vertical facets and re-entrant (upward-reflecting) mirror facets to be made in a single wafer-level wet etch process.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods may include forming a photomask on a (110) silicon wafer substrate, wherein the photomask comprises a periodic array of parallelogram openings, and then performing a timed wet etch on the (110) silicon wafer substrate to form a diffraction grating structure that is etched into the (110) silicon wafer substrate.

Abstract: Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.

Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Abstract: Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and wherein the CMOS wafer has circuitry thereon; forming an unsharpened tip at or near the free end of each cantilever beam; depositing a silicide-forming material over the tip; annealing the wafer to sharpen the tip; and exposing the sharpened tip.

Abstract: A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

Abstract: A seek-scan probe (SSP) memory involves multiple-wafer bonding needing precision small gaps in between. Solder reflow bonding is typically used to join the wafers due to its reliability and ability to hermetically seal. However, solder reflow bonding may not provide a consistently controllable gap due to flowing solder during the bonding process. Thus, a bond stop technique and process is used to provide accurate cantilever to media gap control.

Abstract: Inverted 45° semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45° semiconductor mirror functions to couple light between a plane in the PIC chip defined by thin film layers and a direction normal to a top surface of the PIC chip where it may be generated or collected by an off-chip component, such as a wire terminal. In an exemplary embodiment, a (110) plane of a cubic crystalline semiconductor may provide a 45° facet inverted relative to a (100) surface of the semiconductor from which light is to be emitted. In further embodiments, a (110) plane may be exposed by undercutting a device layer of a semiconductor on insulator (SOI) substrate. Alternatively, a pre-etched substrate surface may be bonded to a handling wafer, thinned, and then utilized for PIC waveguide formation.