Abstract: A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.

Abstract: Variable-resistance devices and methods of forming the same include a variable-resistance layer, formed between a first terminal and a second terminal, that varies in resistance based on an oxygen concentration in the variable-resistance layer. An electrolyte layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage is positioned over the variable-resistance layer. A gate layer is configured to apply a voltage on the electrolyte layer and the variable-resistance layer and is positioned over the electrolyte layer.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 ?. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 ?. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.

Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: This method comprises: a first step for raising the temperature of an object on which a film is being formed to at least 200° C. and changing from a first state in which a film-forming material and a carrier gas are supplied to the object on which the film is being formed to deposit the film-forming material on the object on which the film is being formed to a second state in which the supply of the film-forming material is eliminated from the first state; and a second step for raising the temperature of the object on which the film is being formed to at least 200° C. and changing from a third state in which hydrogen gas and a carrier gas are supplied to the object on which the film is being formed to reduce the film-forming material to a fourth state in which the supply of the hydrogen gas is eliminated from the third state. The film-forming material is any one material selected from the group consisting of Al(CxH2x+1)3, Al(CxH2x+1)2H, and Al(CxH2x+1)2Cl.

Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.

Abstract: Methods of forming capacitors include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: Capacitors and methods of forming the same include forming an oxygenated dielectric layer on a first conductive layer. A second conductive layer is formed on the oxygenated dielectric layer. The oxygenated dielectric layer is heated to release the oxygen from the oxygenated dielectric layer and to oxidize the first and second conductive layers at interfaces between the dielectric layer and the first and second conductive layers, forming barrier layers at the interfaces.

Abstract: A memory device including a via opening through a dielectric layer and an inert electrode having a conformal thickness present on sidewalls but recessed from the top of the via and a base surface of the via opening through the dielectric layer. A metal oxide layer provides a filament forming layer for the memory device and is present in direct contact with the inert electrode. The metal oxide layer also has a conformal thickness and has vertically orientated portions on the portion of the inert electrode overlying the sidewalls of the via opening, and horizontally orientated portions on the portion of the inert electrode overlying the base of the via opening. A reactive electrode is in direct contact with the metal oxide layer. Switching of the memory device includes a laterally orientated direction across the vertically orientated portion of the metal oxide layer in regions not modified by patterning of the conformal metal-oxide layer.

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 ?. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

Abstract: A memory device including a via opening through a dielectric layer and an inert electrode having a conformal thickness present on sidewalls but recessed from the top of the via and a base surface of the via opening through the dielectric layer. A metal oxide layer provides a filament forming layer for the memory device and is present in direct contact with the inert electrode. The metal oxide layer also has a conformal thickness and has vertically orientated portions on the portion of the inert electrode overlying the sidewalls of the via opening, and horizontally orientated portions on the portion of the inert electrode overlying the base of the via opening. A reactive electrode is in direct contact with the metal oxide layer. Switching of the memory device includes a laterally orientated direction across the vertically orientated portion of the metal oxide layer in regions not modified by patterning of the conformal metal-oxide layer.