Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.

Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

Abstract: Capacitors and methods of forming the same include forming an oxygenated dielectric layer on a first conductive layer. A second conductive layer is formed on the oxygenated dielectric layer. The oxygenated dielectric layer is heated to release the oxygen from the oxygenated dielectric layer and to oxidize the first and second conductive layers at interfaces between the dielectric layer and the first and second conductive layers, forming barrier layers at the interfaces.

Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: Methods of forming capacitors include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Abstract: A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH3). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.

Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more metals. The resistive switching memory stack further includes a metal oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more metal oxides. The resistive switching memory stack also includes a top electrode, disposed over the metal oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.

Abstract: A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Abstract: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.