Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

Abstract: A transmitter may include a pre-driver and a main driver. The pre-driver may be configured to generate a pull-up signal and a pull-down signal in response to an enabling signal and a first data. The main driver may receive an external voltage and a ground voltage. The main driver may be configured to generate a transmission data in response to the pull-up signal and the pull-down signal. The pull-up signal and the pull-down signal may be enabled to a voltage level higher than the external voltage applied to the main driver.

Abstract: Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract: A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.

Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Abstract: A semiconductor apparatus includes a test voltage application unit, a first pad and a second pad. The test voltage application unit is configured to apply a test voltage to first and second TSVs in response to a test mode signal. The first pad is configured to output a first test signal outputted from the first TSV. And the second pad is configured to output a second test signal outputted from the second TSV.

Abstract: A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.

Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Abstract: A semiconductor apparatus having a data bit inversion function and, the semiconductor apparatus including a first semiconductor chip and a second semiconductor chip electrically coupled to the first semiconductor chip, wherein the first semiconductor chip may be configured to receive data and a data bit inversion flag, and transfer the data to the second semiconductor chip, and the second semiconductor chip may be configured to invert and store the data, which is transferred from the first semiconductor chip, according to to the data bit inversion flag.

Abstract: A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract: A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.

Abstract: A semiconductor apparatus includes a test voltage application unit, a first pad and a second pad. The test voltage application unit is configured to apply a test voltage to first and second TSVs in response to a test mode signal. The first pad is configured to output a first test signal outputted from the first TSV. And the second pad is configured to output a second test signal outputted from the second TSV.