Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.

Abstract: A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

Abstract: Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

Abstract: A semiconductor device includes: first to Nth input terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kth input terminal (where K is an integer ranging from 1 to N?1) is defective among the first to Nth input terminals, (K+1)th to Nth input terminals receive signals of Kth to (N?1)th input terminals, respectively, and the redundant input terminal receives a signal of the Nth input terminal.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

Abstract: Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.

Abstract: A transmitter may include a pre-driver and a main driver. The pre-driver may be configured to generate a pull-up signal and a pull-down signal in response to an enabling signal and a first data. The main driver may receive an external voltage and a ground voltage. The main driver may be configured to generate a transmission data in response to the pull-up signal and the pull-down signal. The pull-up signal and the pull-down signal may be enabled to a voltage level higher than the external voltage applied to the main driver.

Abstract: Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Abstract: In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

Abstract: A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.

Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Abstract: A semiconductor apparatus includes a test voltage application unit, a first pad and a second pad. The test voltage application unit is configured to apply a test voltage to first and second TSVs in response to a test mode signal. The first pad is configured to output a first test signal outputted from the first TSV. And the second pad is configured to output a second test signal outputted from the second TSV.

Abstract: A semiconductor apparatus may include a semiconductor chip, and the semiconductor chip may include a first pad, a second pad, and a bump. The first pad may be configured to receive a signal from an external device, and the second pad may include first and second metal layers electrically isolated from each other. The bump may be stacked over the second pad, and may be configured to receive a signal from a controller chip.

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.