Patents by Inventor Joo-young Lee

Joo-young Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200233594
    Abstract: A memory system and an operating method thereof are disclosed. An operating method of a memory system including a nonvolatile memory device and a controller configured to control the nonvolatile memory device includes the controller updating original data of firmware stored in the nonvolatile memory device, the controller transmitting a notification signal, which notifies a host device of completion of the updating of the original data, to the host device when the updating of the original data is completed, and the controller updating backup data of the firmware stored in the nonvolatile memory device after the notification signal is transmitted.
    Type: Application
    Filed: September 12, 2019
    Publication date: July 23, 2020
    Inventor: Joo Young LEE
  • Publication number: 20200211440
    Abstract: A method of driving a foldable display device, which includes a first display panel and a second display panel that are foldable onto each other, includes detecting a first gaze angle of a viewer with respect to the first display panel and a second gaze angle of the viewer with respect to the second display panel, determining a first red, green, blue (RGB) luminance ratio corresponding to the first gaze angle and a second RGB luminance ratio corresponding to the second gaze angle based on a mapping table that stores expected gaze angles and optimal RGB luminance ratios mapped to the expected gaze angles, performing a first color shifting operation on the first display panel based on the first RGB luminance ratio, and performing a second color shifting operation on the second display panel based on the second RGB luminance ratio.
    Type: Application
    Filed: December 3, 2019
    Publication date: July 2, 2020
    Inventors: Joo-Young LEE, Young Nam YUN
  • Publication number: 20200210295
    Abstract: A memory system includes: a memory device including a master block and a back-up master block; and a controller suitable for performing a boot operation by using boot data that is read from the master block or the back-up master block, wherein the controller includes: a booting manager suitable for reading boot data from the back-up master block when an operation of reading the boot data from the master block failed; and a test read manager suitable for performing a test read operation on the back-up master block whenever the number of times that the boot data is read reaches a threshold, and performing a recovery operation on the back-up master block when the test read operation is fails.
    Type: Application
    Filed: October 7, 2019
    Publication date: July 2, 2020
    Inventors: Joo-Young LEE, Chang-Han KIM
  • Publication number: 20200211156
    Abstract: An imaging apparatus an image sensor which generates a reference image data of a reference area that includes a measuring area in which a display panel is positioned and an image processor which determines the measuring area by analyzing luminance of the reference image data and generates a crop image data that includes a measuring image data of the measuring area.
    Type: Application
    Filed: December 9, 2019
    Publication date: July 2, 2020
    Inventors: Jonguk BANG, Joo-Young LEE, Jinwon KIM, Sun Hyang SONG, Myoung Hee LEE
  • Publication number: 20200211665
    Abstract: A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map.
    Type: Application
    Filed: October 9, 2019
    Publication date: July 2, 2020
    Inventor: Joo-Young LEE
  • Publication number: 20200192796
    Abstract: A memory system includes a memory device; a short super block detecting unit suitable for forming, when one or more initial bad blocks remain in an original super block after a re-mapping operation is performed and a number of the initial bad blocks is equal to or less than a predetermined threshold value within the original super block, a short super block with memory blocks included in the original super block; a bitmap generating unit suitable for generating a bitmap representing whether each of the memory blocks included in the short super block is a normal block or an initial bad block; and a processor suitable for controlling the memory device to simultaneously perform a normal operation on normal blocks among the memory blocks included in the short super block based on the bitmap.
    Type: Application
    Filed: October 11, 2019
    Publication date: June 18, 2020
    Inventor: Joo-Young LEE
  • Patent number: 10684798
    Abstract: A memory controller includes a flash translation layer configured to output a descriptor including a command and physical information and logical information associated with the command, and a flash interface layer configured to receive the descriptor, individually store the command, the physical information, and the logical information that are included in the descriptor, adjust a queue of the command, and output the command to a memory device according to an adjusted queue of the command.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventor: Joo Young Lee
  • Publication number: 20200183832
    Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.
    Type: Application
    Filed: July 25, 2019
    Publication date: June 11, 2020
    Inventors: Joo Young LEE, Ki Duck KIM, Jea Young ZHANG
  • Publication number: 20200175668
    Abstract: Disclosed herein are a method and apparatus for measuring video quality based on a perceptually sensitive region. The quality of video may be measured based on a perceptually sensitive region and a change in the perceptually sensitive region. The perceptually sensitive region includes a spatial perceptually sensitive region, a temporal perceptually sensitive region, and a spatio-temporal perceptually sensitive region. Perceptual weights are applied to a detected perceptually sensitive region and a change in the detected perceptually sensitive region. Distortion is calculated based on the perceptually sensitive region and the change in the perceptually sensitive region, and a result of quality measurement for a video is generated based on the calculated distortion.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Se-Yoon JEONG, Dae-Yeol LEE, Seung-Hyun CHO, Hyunsuk KO, Youn-Hee KIM, Jong-Ho KIM, Jin-Wuk SEOK, Joo-Young LEE, Woong LIM, Hui-Yong KIM, Jin-Soo CHOI
  • Publication number: 20200167232
    Abstract: A method for operating a memory system which includes a memory device and a controller for controlling the memory device, the operating method includes searching one or more open memory blocks included in the memory device, when a booting operation is performed; detecting one or more erase pages included in each of the open memory blocks; checking an erase threshold voltage distribution corresponding to each of the erase pages; counting a number of first bad pages among the erased pages based on the erase threshold voltage distribution; and switching a first open memory block including the first bad pages among the open memory blocks into a first closed memory block when the number of first bad pages is equal to or greater than a first threshold value.
    Type: Application
    Filed: October 8, 2019
    Publication date: May 28, 2020
    Inventor: Joo-Young LEE
  • Publication number: 20200159457
    Abstract: A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.
    Type: Application
    Filed: September 26, 2019
    Publication date: May 21, 2020
    Inventor: Joo-Young LEE
  • Publication number: 20200161308
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Applicant: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Inventors: Jin-A KIM, Yong-Kwan Kim, Se-Keun Park, Joo-Young Lee, Cha-Won Koh, Yeong-Cheol Lee
  • Publication number: 20200162736
    Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In image encoding, encoding using multiple quantization parameters is performed on a transform coefficient. Two quantized coefficients are generated through encoding that uses two quantization parameters. Based on the two quantized coefficients, a quantized coefficient difference is generated. Information about the quantized coefficient difference is transmitted from an encoding apparatus to a decoding apparatus through binary encoding. The information about the quantized coefficient difference may be selectively transmitted. By means of the information about the quantized coefficient difference, a high-quality video may be provided.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 21, 2020
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jin-Wuk SEOK, Hyunsuk KO, Youn-Hee KIM, Jong-Ho KIM, Joo-Young LEE, Woong LIM, Se-Yoon JEONG, Seung-Hyun CHO, Hui-Yong KIM, Jin-Soo CHOI
  • Publication number: 20200153861
    Abstract: Disclosed herein are a decoy apparatus and a method for expanding a fake attack surface using a deception network. The method includes determining, by a protected server, whether a packet is a target to be processed when the packet is received; converting, by the protected server, the packet and transmitting, by the protected server, the converted packet to the decoy apparatus of the deception network when the packet is determined not to be such a target; receiving, by the protected server, a response packet from a decoy virtual machine included in the decoy apparatus as a reply to the converted packet; and modifying, by the protected server, the response packet and transmitting, by the protected server, the modified response packet to the source from which the packet was transmitted, in order to expand the fake attack surface.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 14, 2020
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyung-Min PARK, Dae-Sung MOON, Ki-Jong KOO, Ik-Kyun KIM, Samuel WOO, Joo-Young LEE
  • Publication number: 20200135270
    Abstract: A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.
    Type: Application
    Filed: June 17, 2019
    Publication date: April 30, 2020
    Inventors: Joo Young LEE, Hoe Seung JUNG
  • Publication number: 20200136800
    Abstract: A method of generating a cryptographic algorithm according to one embodiment of the present disclosure includes generating one or more key tables on the basis of a seed value; generating a first transformation function that converts an input bit string, which is input to one of input branches of a Feistel structure, into a first random bit string having a length that extends beyond a length of the input bit string; generating a second transformation function that converts a second random bit string generated by referencing the one or more key tables into a third random bit string having a length that is the same as the length of the input bit string; and generating a block cryptographic algorithm of a Feistel structure which includes a round function to which the one or more key tables, the first transformation function, and the second transformation function are applied.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Inventors: Duk-Jae Moon, Kyu-Young Choi, Joo-Young Lee
  • Publication number: 20200136801
    Abstract: A method of generating a cryptographic algorithm includes generating at least one key table on the basis of a seed value; generating, by using a round tweak bit string and an input bit string that is input to one of input branches of a Feistel structure, a first transformation function converting the input bit string into a first random bit string having a length that extends beyond a length of the input bit string, generating a second transformation function converting a second random bit string generated by referencing the one or more key tables into a third random bit string having a length that is the same as the length of the input bit string, and generating a block cryptographic algorithm of a Feistel structure which includes a round function to which the one or more key tables, the first transformation function, and the second transformation function are applied.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Inventors: Duk-Jae Moon, Kyu-Young Choi, Joo-Young Lee
  • Publication number: 20200101194
    Abstract: Provided are a hydrogel composition with high viscoelasticity and a bioink composition including the hydrogel composition. The hydrogel composition according to an embodiment is composed of natural biocompatible substances and thus is not toxic, but has high viscosity, resulting in high mechanical stability or long persistence. Thus, the hydrogel composition may be usefully utilized as a bioink composition for bioprinting, a support in tissue engineering, or a soft tissue filler.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 2, 2020
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Heon KIM, Joo Young LEE, Seung Ja OH
  • Publication number: 20200107023
    Abstract: Disclosed herein is a context-adaptive entropy model for end-to-end optimized image compression. The entropy model exploits two types of contexts. The two types of contexts are a bit-consuming context and a bit-free context, respectively, and these contexts are classified depending on the corresponding context requires the allocation of additional bits. Based on these contexts, the entropy model may more accurately estimate the distribution of each latent representation using a more generalized form of entropy models, thus improving compression performance.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Joo-Young LEE, Seung-Hyun CHO, Seung-Kwon BEACK, Hyunsuk KO, Youn-Hee KIM, Jong-Ho KIM, Jin-Wuk SEOK, Woong LIM, Se-Yoon JEONG, Hui-Yong KIM, Jin-Soo CHOI
  • Publication number: 20200097408
    Abstract: A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Mth subpage data of the first page data is completed, the cache buffer receives and caches Mth subpage data of second page data from the controller, where M is a positive number less than N.
    Type: Application
    Filed: July 26, 2019
    Publication date: March 26, 2020
    Inventors: Joo Young LEE, Hoe Seung JUNG