Abstract: A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.

Abstract: A controller configured to control memory chips in communication with the controller is provided. The controller comprises: a host interface configured to receive a request from a host; an address mapper configured to, upon receipt of both a turbo write request for writing data to one or more high-speed storage blocks at a high speed to and a normal write request for writing data to one or more storage blocks at a lower speed, allocate a first plane including a memory block configured to perform write operations in a single level cell mode at the high speed to a first plane group in order to respond to the turbo write request, and allocate a second plane to a second plane group at the slower speed in order to respond to the normal write request; and a memory interface configured to control the memory chips.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

Abstract: A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map.

Abstract: A memory controller for controlling one or more memory devices is provided. The memory controller includes a storage area manager and an operation controller in communication with the storage area manager. The storage area manager is configured to determine a number of super block groups having a predetermined size based on a number of the memory devices connected to the memory controller through a channel, allocate at least one memory device to each of the super block groups, and allocate at least two memory blocks included in the at least one memory device in each of the super block groups as a super block. The operation controller is configured to control the at least one memory device in each of the super block groups to store data in the super block or to read data stored in the super block.

Abstract: Disclosed herein are a method and apparatus for compressing learning parameters for training of a deep-learning model and transmitting the compressed parameters in a distributed processing environment. Multiple electronic devices in the distributed processing system perform training of a neural network. By performing training, parameters are updated. The electronic device may share the updated parameter thereof with additional electronic devices. In order to efficiently share the parameter, the residual of the parameter is provided to the additional electronic devices. When the residual of the parameter is provided, the additional electronic devices update the parameter using the residual of the parameter.

Abstract: The present invention relates to a composition including an anthocyanin-fucoidan complex formed by ionic bond between anthocyanin and fucoidan as an active ingredient, and more particularly, it is confirmed that the anthocyanin-fucoidan complex in which anion of the fucoidan, which is a natural extract having high biocompatibility and biodegradability, is ionically bonded with a cation of the anthocyanin improves the stability and the solubility of the anthocyanin even in acidic conditions in vivo, thereby increasing the immune activity in vivo and therefore it is intended to provide the anthocyanin-fucoidan complex as an immune enhancer, an immune-cancer agent and an anticancer adjuvant composition for alleviating side effects of anti-cancer agents.

Abstract: A memory system includes: a memory device; a command queue queuing a program descriptor and a first read descriptor, and sequentially outputting the descriptors; a program manager performing an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address when a program operation performed on a first physical address fails; a fail managing buffer storing the first physical address for the failed program operation; a queue manager deleting the first read descriptor from the command queue and outputting an exception signal, when a physical address of the first read descriptor is the same as the first physical address; and a descriptor generator generating a second read descriptor including the second physical address in response to the exception signal and enqueuing the second read descriptor in the command queue, when the error handling operation passed.

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory controller may include a storage area manager and a write operation controller. The storage area manager may allocate a plurality of memory devices to a first group and a second group in response to a storage area setting command. The write operation controller may control a group selected from the first group and the second group according to a type of a write request to store write data. At least one memory devices in the first group includes memory blocks storing n data bits. At least one memory devices in the second group includes memory blocks storing m data bits.

Abstract: A storage device having an improved operation speed includes: a plurality of memory devices each including a plurality of memory blocks; and a memory controller configured to allocate a super block including at least two memory blocks included in different memory devices among the plurality of memory blocks, read state information in a memory block state information table indicating whether each of the plurality of memory blocks is a bad block or a normal block, and adjust the size of write data that is data to be stored in a selected stripe among a plurality of stripes included in the super block, based on the state information in the memory block state information table.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. A virtual frame is generated by a video generation network including a generation encoder and a generation decoder. The virtual frame is used as a reference frame in inter prediction for a target. Further, a video generation network for inter prediction may be selected from among multiple video generation networks, and inter prediction that uses the selected video generation network may be performed.

Abstract: A method and apparatus for image compression using a latent variable are provided. The multiple components of the latent variable may be sorted in order of importance. Through sorting, when the feature information of only some of the multiple components is used, the quality of a reconstructed image may be improved. In order to generate a latent variable, the components of which are sorted in order of importance, learning may be performed in various manners. Also, less important information may be eliminated from the latent variable, and processing, such as quantization, may be applied to the latent variable. Through elimination and processing, the amount of data for the latent variable may be reduced.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In quantization and dequantization, multiple quantization methods and multiple dequantization methods may be used. The multiple quantization methods include a variable-rate step quantization method and a fixed-rate step quantization method. The variable-rate step quantization method may be a quantization method in which an increment in a quantization step depending on an increase in a value of a quantization parameter by 1 is not fixed. The fixed-rate step quantization method may be a quantization method in which the increment in the quantization step depending on the increase of the value of the quantization parameter by 1 is fixed.

Abstract: Provided is a method for setting a thermal comfort scale of an age-specific perceived temperature of residents living in a certain area based on an experiment exposed to thermal stress environment in an artificial climate chamber.

Abstract: A memory system includes: a memory device including a memory block, a page buffer, and first and second memory dies; a write buffer suitable for temporarily storing first and second data; a program managing unit suitable for controlling the memory device to sequentially perform first and second program operations on the memory block with the first and second data; a buffer managing unit suitable for managing the write buffer based on a scatter-gather scheme; a failure processing unit suitable for forcing the second program operation to fail, when the first program operation is a failure; and an error handling unit suitable for controlling the program managing unit to perform the first and second program operations again for the first and second data that are temporarily stored in the write buffer when the second program operation is forced to fail.

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

Abstract: A memory system includes a nonvolatile memory device; In an embodiment, a memory system comprising: a nonvolatile memory device; a working memory configured to store a first layer and a second layer as firmwares, each of which drives the nonvolatile memory device; a control component configured to control the nonvolatile memory device based on the firmwares; a buffer memory configured to store a first table which is managed by the first layer and a second table which is managed by the second layer; and a memory controller configured to store a descriptor for setting information of the nonvolatile memory device, and interface with the nonvolatile memory device based on control of the control component, wherein the second layer stores position information of the descriptor in the second table, and wherein the first layer accesses the memory controller by referring to the second table.

Abstract: There are provided a memory controller and an operating method thereof. The memory controller includes a host interface layer for receiving a host program request and a host read request, a flash translation layer for generating and outputting a program command and a plurality of program addresses in response to the host program request, checking a program progress state for a program address corresponding to a target read address when the target read address corresponding to the host read request is included in the program addresses, and controlling a read operation on the target read address according to whether a program operation on the program address corresponding to the target read address has been completed, and a flash interface layer for transmitting a command and addresses, which are output from the flash translation layer, to a memory device.

Abstract: A memory system and an operating method thereof are disclosed. An operating method of a memory system including a nonvolatile memory device and a controller configured to control the nonvolatile memory device includes the controller updating original data of firmware stored in the nonvolatile memory device, the controller transmitting a notification signal, which notifies a host device of completion of the updating of the original data, to the host device when the updating of the original data is completed, and the controller updating backup data of the firmware stored in the nonvolatile memory device after the notification signal is transmitted.