Abstract: Provided are a hydrogel composition with high viscoelasticity and a bioink composition including the hydrogel composition. The hydrogel composition according to an embodiment is composed of natural biocompatible substances and thus is not toxic, but has high viscosity, resulting in high mechanical stability or long persistence. Thus, the hydrogel composition may be usefully utilized as a bioink composition for bioprinting, a support in tissue engineering, or a soft tissue filler.

Abstract: Disclosed herein is a context-adaptive entropy model for end-to-end optimized image compression. The entropy model exploits two types of contexts. The two types of contexts are a bit-consuming context and a bit-free context, respectively, and these contexts are classified depending on the corresponding context requires the allocation of additional bits. Based on these contexts, the entropy model may more accurately estimate the distribution of each latent representation using a more generalized form of entropy models, thus improving compression performance.

Abstract: A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Mth subpage data of the first page data is completed, the cache buffer receives and caches Mth subpage data of second page data from the controller, where M is a positive number less than N.

Abstract: Disclosed are a method and apparatus for searching for an attack path. The apparatus generates an attack graph, generates an attack graph ontology, generates a semantic attack graph by imparting semantics to the attack graph on the basis of the attack graph ontology, and searches for the attack path on the basis of the semantic attack graph.

Abstract: A data storage device includes: a storage configured to generate a program completion signal when a data chunk is completely programmed; a buffer memory having a plurality of buffer regions configured to cache a plurality of data chunks, respectively; and a controller configured to receive a data chunk from a host device while a previously cached data chunk in the buffer memory is programmed to the storage; cache the received data chunk into the buffer memory; delete the programmed data chunk from the buffer memory in response to the program completion signal; receive a new data chunk from the host device; and cache the received new data chunk in an empty buffer region of the buffer memory.

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, word lines, a doped junction, bit line structures, and buried contacts. The substrate has active regions. The word lines extend across the active regions. The doped junction has impurities and is arranged at the active regions, and includes first junctions and second junctions, each first junction arranged at a central portion of one of the active regions and each second junction arranged at an end portion of another one of the active regions, a buried semiconductor layer being included in each second junction. The bit line structures contact with a respective one of the first junctions. The buried contacts are arranged in a matrix shape, each contacting with a respective one of the second junctions and the included buried semiconductor layer and simultaneously contacting with a charge storage for storing data.

Abstract: A memory system includes a controller suitable for providing first data, a cache program command corresponding to the first data, second data, and a normal program command corresponding to the second data; and a memory device suitable for programming the first data to a target die according to the cache program command, setting the target die to a normal state after the program operation for the first data is completed, and programming the second data to the target die according to the normal program command.

Abstract: A data processing system comprising: a host; and a memory system comprising a nonvolatile memory device and a controller suitable for controlling the nonvolatile memory device, wherein the controller comprises: a first reset circuitry suitable for loading firmware from the nonvolatile memory device to a volatile memory, and setting a reset default status; a second reset circuitry suitable for determining whether a reason for a reset request coincides with the reset default status, when the reset request is received from the host, and resetting the memory system; and a firmware load determination circuitry suitable for determining whether to reload the firmware by checking the reset default status.

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.

Abstract: A memory system includes a memory device including a plurality of dies each including one or more flush blocks and one or more multi-level cell blocks; a controller write buffer; a controller buffer manager configured to buffer host data into the controller rite buffer; a flush block manager configured to control, when a flush command is received, the memory device to perform an interleaved program operation of programming the buffered host data into the flush blocks respectively included in the dies; and a processor configured to control, when a size of the buffered host data reaches a threshold value, the memory device to perform the interleaved program operation of programming the buffered host data into the multi-level cell blocks respectively included in the dies.

Abstract: A data storage device includes a storage unit; and a controller configured to select a write mode by analyzing a tendency of commands received from a host device, and operate in the selected write mode to write data to the storage or to read data from the storage.

Abstract: A memory system includes: a memory device including a first memory buffer and a second memory buffer; a controller write buffer; a memory buffer manager suitable for controlling the memory device to buffer first data stored in the first memory buffer into the second memory buffer while the memory device programs, in a program operation, the first data into a memory block; a controller buffer manager suitable for deleting the first data stored in the controller write buffer after the memory device buffers the first data into the second memory buffer; and a failure processor suitable for controlling the memory device to perform a reprogram operation of reprogramming the first data, when the program operation fails.

Abstract: Disclosed herein are a server apparatus, a client apparatus, and a method for communication based on network address mutation. The method for communication based on network address mutation, performed by the server apparatus and the client apparatus, includes setting the external address of a network interface for receiving a packet from the client apparatus; setting the internal address of a hidden interface in order to forward the packet received through the network interface to the hidden interface; modifying the external address based on a preset network address mutation rule; and communicating with the client apparatus by forwarding the packet, received from the client apparatus based on the modified external address, to the hidden interface.

Abstract: A memory system includes: a non-volatile memory device; a host controller suitable for generating a cache read command for controlling a cache read operation of the non-volatile memory device and at least one other command for controlling at least one other operation of the non-volatile memory device excluding the cache read operation in response to a request received from a host; and a memory controller suitable for controlling an operation of the non-volatile memory device in response to the cache read command and the at least one other command that are inputted from the host controller. The memory controller suitable for checking out the operation of the non-volatile memory device corresponding to a command that is inputted next to the input of the cache read command, and adding a read operation command including a read preparation command or a read end command next to the cache read command.

Abstract: Disclosed is a method and apparatus for encoding/decoding an image. The image encoding apparatus according to an embodiment of the present disclosure may include: an encoding level decision unit determining an encoding level of an input image; a sampling unit outputting an encoding target picture associated with the encoding level determined in the encoding level decision unit; an encoding unit encoding the encoding target picture output from the sampling unit; a reference picture storage unit storing at least one reference picture; and a reconstructed image generation unit generating a reconstructed image corresponding to the input image in association with the encoding level determined in the encoding level decision unit.

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.

Abstract: The semiconductor memory device includes a memory cell array, a page buffer, a cache buffer, and a control logic. The memory cell array includes a plurality of memory blocks. The page buffer senses data of a selected page of the memory cell array. The cache buffer temporarily stores the data sensed by the page buffer. The control logic controls operations of the page buffer and the cache buffer to read data stored in the memory cell array. The control logic controls operations of the page buffer and the cache buffer, based on a cache-normal state of the semiconductor memory device.

Abstract: There are provided a memory controller and an operating method thereof. The memory controller includes a host interface layer for receiving a host program request and a host read request, a flash translation layer for generating and outputting a program command and a plurality of program addresses in response to the host program request, checking a program progress state for a program address corresponding to a target read address when the target read address corresponding to the host read request is included in the program addresses, and controlling a read operation on the target read address according to whether a program operation on the program address corresponding to the target read address has been completed, and a flash interface layer for transmitting a command and addresses, which are output from the flash translation layer, to a memory device.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: A storage device having an improved operation speed includes: a plurality of memory devices each including a plurality of memory blocks; and a memory controller configured to allocate a super block including at least two memory blocks included in different memory devices among the plurality of memory blocks, read state information in a memory block state information table indicating whether each of the plurality of memory blocks is a bad block or a normal block, and adjust the size of write data that is data to be stored in a selected stripe among a plurality of stripes included in the super block, based on the state information in the memory block state information table.