Abstract: A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.

Abstract: Disclosed in an embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a reflective layer disposed on the second electrode and including a first metal; and a nitride of the first metal between the second electrode and the reflective layer.

Abstract: An embodiment provides a semiconductor device comprising: a semiconductor structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, and a plurality of first recesses and second recesses which extend through the second conductive semiconductor layer and the active layer and are arranged up to one region of the first conductive semiconductor layer, a first electrode disposed inside each of the first recesses and second recesses to be electrically connected to the first conductive semiconductor layer, and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer, the active layer, the second conductive semiconductor layer include aluminum, and the number of most adjacent recesses in the plurality of second recesses is fewer than that in the plurality of first recesses and the plurality of second recesses include multiple recesses, each having an area larger than that of each

Abstract: Disclosed in an embodiment is a semiconductor device comprising: a conductive substrate; a semiconductor structure, which is arranged on the conductive substrate, comprises a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and comprises a plurality of recesses which pass through the second conductive type semiconductor layer and the active layer and up to a partial region of the first conductive type semiconductor layer; a first electrode electrically connecting the first conductive type semiconductor layer to the conductive substrate; a second electrode electrically connected to the second conductive type semiconductor layer; and an insulating layer arranged inside the plurality of recesses, wherein the plurality of recesses comprise a first recess extending along the outer surface of the semiconductor structure and a plurality of seco

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: The present invention relates to gene and cell therapy using a cell fusion technology and more particularly, cells overexpressing hemagglutinin neuraminidase (HN) and fusion (F) proteins have effects of enhancing cell fusion with other cells, restoring cell damage through the cell fusion with damaged cells, and transferring a normal gene. Therefore, when a vector including genes encoding the HN and F proteins of the present invention or a cell transformed with the vector is clinically applied to neurodegenerative diseases, muscular diseases, and the like, an effect of reducing the damage of damaged cells through cell fusion can be expected.

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: A charging and discharging apparatus including a temperature measuring device suitable for measuring a temperature of each secondary battery and a cooling fan for cooling secondary batteries by utilizing temperature information using the temperature measuring device, such that a temperature deviation between the secondary batteries, which may occur during charging and discharging in a formation process and a capacity test after a secondary battery assembly process, is provided. The charging and discharging apparatus includes a movable non-contact temperature measuring device and cooling fans of which directions of wind and outputs are individually adjusted based on temperature information measured by the temperature measuring device according to a location in each secondary battery.

Abstract: The present invention relates to a method for activating a secondary battery. The present invention comprises: a primary charging step of charging a secondary battery including a positive electrode, a negative electrode, a separator, and an electrolyte; a room temperature-aging step of storing, at a room temperature, the secondary battery that has undergone the primary charging step; and a high temperature-aging step of storing, at a high temperature, the secondary battery that has undergone the room temperature-aging step, wherein charging/discharging is performed by alternately applying + current and ? current to the secondary battery at the end of the primary charging step. The method for activating a secondary battery according to the present invention includes alternately applying + current and ? current to the secondary battery at the end of the primary charging step to stabilize an SEI film, thereby shortening a following-up aging time.

Abstract: A lift pin module includes a lift pin which includes a head portion disposed at a first end of the lift pin, and a connecting portion disposed at a second end of the lift pin opposite to the first end, the head portion connected to a stage disposed inside a semiconductor process chamber, and the head portion extending in a first direction; an upper weight which includes a side surface with an opening extending in the first direction, the opening configured to receive the lift pin therein, and the upper weight surrounding the connecting portion of the lift pin; and a lower weight screwed to the upper weight, the lower weight disposed below the upper weight.

Abstract: Provided are a method of obtaining a water-fat separation image and a magnetic resonance imaging (MRI) apparatus including a controller configured to obtain first partial k-space data, second partial k-space data, and third partial k-space data, respectively based on a first partial echo signal, a second partial echo signal, and a third partial echo signal, which are magnetic resonance signals corresponding to a plurality of echo times with respect to an object, obtain first reconstruction image data, second reconstruction image data, and third reconstruction image data with respect to the object, respectively based on the first partial k-space data, the second partial k-space data, and the third partial k-space data, and obtain first water image data, first fat image data, and first phase image data of the object, respectively based on the first reconstruction image data, the second reconstruction image data, and the third reconstruction image data, by using a Dixon technique.

Abstract: Disclosed in an embodiment is a semiconductor device comprising: a substrate; a semiconductor structure including a first conductive semiconductor layer and a second conductive semiconductor layer, which are arranged on the substrate, an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, and a recess formed in the second conductive semiconductor layer and the active layer; a first electrode arranged on the semiconductor structure and electrically connected with the first conductive semiconductor layer; a second electrode arranged on the semiconductor structure and electrically connected with the second conductive semiconductor layer; a first pad arranged on the first electrode; and a second pad arranged on the second electrode, wherein the recess separates the second conductive semiconductor layer and the active layer into an active region and an inactive region, the recess extends so as to encompass the active region, and the second pad exten

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

Abstract: A method for manufacturing a cylindrical battery having multiple tabs is provided in which the cylindrical battery includes an electrode assembly, a cylindrical pouch case, an electrode tab protruding to an upper end of the electrode assembly, and an electrode lead welded and electrically connected to the electrode tab, with the electrode tab being plural. The method includes disposing the plurality of electrode tabs on the electrode assembly; winding the electrode assembly into a cylindrical shape; connecting the electrode lead to the plurality of electrode tabs disposed on the upper end of the electrode assembly; inserting the electrode assembly into the cylindrical pouch case to produce a battery cell; connecting, to the cylindrical pouch case, a gas collecting part for collecting gas generated due to charging and discharging of the electrode; and forming a guide part for preventing deformation of the battery cell in the cylindrical pouch case.

Abstract: A light emitting device can include a sapphire substrate; a first conductivity type semiconductor layer disposed on the sapphire substrate; an active layer disposed on the first conductivity type semiconductor layer; a plurality of p-type conductors disposed on the active layer, and separated from each other; a first pad disposed on the first conductivity type semiconductor layer; and a second pad disposed on the plurality of p-type conductors, in which the plurality of p-type conductors are arranged in a first direction, the second pad is spaced apart from the first pad in a second direction, the second direction is perpendicular to the first direction, each of the plurality of p-type conductors has a first width in the first direction and a second width in the second direction, the first width being less than the second width, the plurality of p-type conductors are evenly spaced apart by a first distance in the first direction, and the first distance being less than the first width of each of the plurality