Abstract: An electrode includes a unit body stack part formed by stacking at least one basic unit having a four-layer structure in which a first electrode, a first separator, a second electrode and a second separator are sequentially stacked. Each surface of the first separator and the second separator is coated with a coating material having adhesiveness, and the basic unit adheres to an adjacent radial unit in the unit body stack part. The electrode assembly of allows a heating and pressing process to be performed prior to a primary formation process so that a separator of one basic unit and a first electrode of the other basic unit to be adhered and fixed by a coating material coated on the separator, and thus a bending phenomenon caused by a difference in electrode expansion rates in a charging/discharging process is prevented.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: The present invention is a method for manufacturing a secondary battery. An electrode assembly and an electrolyte are accommodated into a body of a battery case. The body of the battery case has an accommodation part and a gas pocket part, and a passage that extends from the accommodation part to the outside discharges an internal gas from the accommodation part through the gas pocket part. The battery case is seated in a seating step on a support block, which has an inclined part on a side surface thereof, to support the battery case. The body is pressed to discharge a gas accommodated in the accommodation part through the gas pocket part in the battery case. This method allows easy discharging of internal gas while reducing discharge of the electrolyte with the gas.

Abstract: A battery cell degassing apparatus for degassing a battery cell having a gas pocket, which includes a chamber cover to which the battery cell is detachably mounted, a vacuum chamber coupled to the chamber cover and configured to accommodate the battery cell in a vacuum environment, the chamber cover being slidable in a horizontal direction with respect to the vacuum chamber, a piercing unit provided at the vacuum chamber to pierce a part of the gas pocket, and a pressing unit provided at the vacuum chamber to be spaced apart from the piercing unit and configured to flatten an upper surface and a lower surface of the battery cell and to discharge a gas inside the battery cell to the outside of the battery cell is provided.

Abstract: An embodiment discloses a semiconductor element comprising: a first conductive semiconductor layer; a second conductive semiconductor layer; an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; and an electron blocking layer arranged between the second conducive semiconductor layer and the active layer, wherein the section of the first conductive semiconductor layer decreases in a first direction, the electron blocking layer has an area in which the section thereof increases in the first direction, and the first direction is defined from the first conductive semiconductor layer to the second conductive semiconductor layer.

Abstract: One embodiment comprises: a semiconductor substrate; a pattern layer disposed on the semiconductor substrate and comprising a plurality of patterns that are spaced apart from each other; a nitride semiconductor layer disposed on the pattern layer; and a semiconductor substrate disposed on the nitride semiconductor layer and comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, wherein the thermal conductivity of the pattern layer is higher than the thermal conductivity of the semiconductor substrate and the thermal conductivity of the semiconductor structure.

Abstract: Disclosed in an embodiment is a semiconductor device including a light-emitting structure which includes a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a recess passing through the second conductive semiconductor layer, the active layer, and a portion of the first conductive semiconductor layer, a conductive layer electrically connected to the second conductive semiconductor layer, and a bonding pad disposed to be spaced apart from the light-emitting structure, wherein the active layer is divided into an inactive region and an active region by the recess, the conductive layer is electrically connected to the active region, and the conductive layer includes a stepped portion overlapping the recess in a vertical direction.

Abstract: The present invention relates to memory apparatuses and an operating methods using a heterogeneous memory array. An operation method of a memory apparatus using a heterogeneous memory array according to an embodiment of the present invention includes dividing an input bit into at least one data bit according to a mode bit, and writing the divided data bits in each cell of the memory array by using a cell level of the memory array which is configured according to the mode bit.

Abstract: A top cap for a secondary battery includes a circumferential area which defines an outer circumferential surface of the top cap, a central area which defines a central portion of the top cap, a connection area which connects the circumferential area to the central area, and a protrusion area which protrudes downward from the circumferential area, the central area, or the connection area. The top cap is assembled with a battery case, an electrode assembly positioned therein, and a through-hole formation member to form a secondary battery, in which at least a portion of the protrusion area of the top cap is positioned within a through-hole of the through-hole formation member.

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

Abstract: Disclosed in one embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; a second electrode electrically connected with the second conductive semiconductor layer; a reflective layer arranged on the second electrode; and a capping layer arranged on the reflective layer and including a plurality of layers, wherein the capping layer includes a first layer directly arranged on the reflective layer and the first layer includes Ti.

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.

Abstract: A temperature measurement device suitable for measuring the temperature of each secondary battery to consider a temperature deviation between secondary batteries that may occur during charging/discharging in the formation process and capacity test after the secondary battery assembly process, and a charge/discharge apparatus including the temperature measurement device are provided. The temperature measurement device is for measuring a temperature of at least one of a plurality of secondary batteries arranged along an X-axis direction, spaced apart from one another, in a standing position, and includes a non-contact temperature sensor unit which is insertable into a spacing between adjacent secondary batteries to measure the temperature of the secondary battery that the non-contact temperature sensor unit faces in a non-contact manner, and a Z-axis transfer device which inserts the non-contact temperature sensor unit into the spacing downward from above the secondary batteries in a Z-axis direction.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

Abstract: A vertical tunneling field-effect transistor (TFET) and a method of fabricating the same are provided. More particularly, the vertical TFET includes a source layer that is disposed on a substrate, has a protrusion portion extending upwardly, and is doped at a uniform concentration in an entire region thereof including the protrusion portion, a channel pattern that covers the protrusion portion of the source layer on the source layer and exposes the remainder of the source layer, a drain pattern that overlaps the channel pattern on the channel pattern and is doped to have a concentration gradient, a gate insulating film that covers the source layer, the channel pattern, and the drain pattern, and a gate electrode that is disposed around the channel pattern on the gate insulating film.

Abstract: A gene and cell therapy using a cell fusion technology is proposed. Cells overexpressing hemagglutinin neuraminidase (HN) and fusion (F) proteins have effects of enhancing cell fusion with other cells, restoring cell damage through the cell fusion with damaged cells, and transferring a normal gene. Therefore, when a vector including genes encoding the HN and F proteins of the present invention or a cell transformed with the vector is clinically applied to neurodegenerative diseases, muscular diseases, and the like, an effect of reducing the damage of damaged cells through cell fusion can be expected.

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.