Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: This application relates to an absolute position detection device and detection method of a rotating body. In one aspect, the device includes first row magnets coupled to a rotating body to rotate together and having n pole pairs, and second row magnets coupled to the rotating body to rotate together and having (n+1) pole pairs. The device also includes a first Hall sensor installed adjacent to the first row magnets and configured to detect a change in magnetism according to rotation of the first row magnets. The device further includes a second Hall sensor installed adjacent to the second row magnets and configured to detect a change in magnetism according to rotation of the second row magnets. The device further includes a controller configured to measure an absolute position of the rotating body using signals output from the first and second Hall sensors.

Abstract: This application relates to an absolute position detection device and detection method of a rotating body using a magnetic material. The device may include magnets coupled to a rotating body and configured to rotate together and having n pole pairs, wherein n is a natural number and (n+1) magnetic materials arranged adjacent to the magnets, spaced apart from each other by a predetermined interval, and configured to rotate together with the rotating body. The device may also include a first Hall sensor spaced apart from the magnets, installed to allow the magnetic materials to rotate in a space between the first Hall sensor and the magnets and configured to output a first signal based on the magnets when the magnetic materials approach the first Hall sensor. The device may further include a controller configured to measure an absolute position of the rotating body using the first signal.

Abstract: The present invention relates to an artificial blood vessel comprising a shape-memory polymer, and a vascular anastomotic member formed of a shape-memory polymer. An artificial blood vessel according to an embodiment of the present invention comprises a shape-memory polymer including photo-crosslinkable functional groups, the artificial blood vessel thus provided having a fusion point suitable for in vivo transplantation. Also, provided is a vascular anastomotic member which comprises a shape-memory polymer including photo-crosslinkable functional groups, and thus has a fusion point suitable for in vivo transplantation.

Abstract: A semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer; a first electrode provided on a first surface of the first semiconductor layer; a second electrode provided on a first surface of the second semiconductor layer, the active layer being provided between the first surface of the first semiconductor layer and a second surface of the second semiconductor layer that is opposite to the first surface of the second semiconductor layer; a first insulation layer provided on the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and a side surface of the active layer; a first cover electrode provided on the first electrode; a second cover electrode provided on the second electrode, a second insulation layer provided on the first cover electrode, the second cover electrode, and the first insulation layer, wherein: the second insulation layer includes a first opening over the

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

Abstract: Disclosed is a method for manufacturing a semiconductor light emitting device. The method includes a first step of forming a semiconductor structure in which a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer are sequentially stacked; and a second step of forming a mesa structure by removing a portion of each of the second conductive-type semiconductor layer and the active layer, wherein the second step includes: forming a mesa structure by etching a portion of each of the second conductive-type semiconductor layer and the active layer using a plasma etching process; and performing an atomic layer etching process on a surface of the mesa structure formed by the plasma etching process.

Abstract: It is a technical object of the present invention to provide a boot clamping structure for a constant velocity joint that can securely fasten a clamp and a boot so that the clamp and the boot do not run against each other. To this end, the boot clamping structure for a constant velocity joint of the present invention is a boot clamping structure for a constant velocity joint for fastening both ends of a boot using a clamp, and includes a main pressing portion that is provided to be protruded in a first direction toward the boot on an inner circumferential surface of the clamp.

Abstract: The present invention relates to a nasolacrimal duct insertion member comprising a shape memory polymer for treatment of nasolacrimal duct obstruction/stenosis, wherein the shape memory polymer comprises a crosslinkable functional group, such that the nasolacrimal duct insertion member has a melting point suitable for implantation into a living body.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: The present invention relates to gene and cell therapy using a cell fusion technology and more particularly, cells overexpressing hemagglutinin neuraminidase (HN) and fusion (F) proteins have effects of enhancing cell fusion with other cells, restoring cell damage through the cell fusion with damaged cells, and transferring a normal gene. Therefore, when a vector including genes encoding the HN and F proteins of the present invention or a cell transformed with the vector is clinically applied to neurodegenerative diseases, muscular diseases, and the like, an effect of reducing the damage of damaged cells through cell fusion can be expected.

Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

Abstract: Disclosed in an embodiment is a semiconductor device comprising: a substrate; a light emitting structure including a first conductive semiconductor layer and a second conductive semiconductor layer, which are arranged on the substrate, an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer, a concave part that is concave on the second conductive semiconductor layer toward the first conductive semiconductor layer, and a recess; a first electrode arranged on the concave part and electrically connected to the first conductive semiconductor layer; a second electrode arranged on the light emitting structure and electrically connected to the second conductive semiconductor layer; a first pad arranged on the first electrode; and a second pad arranged on the second electrode, wherein the recess separates the second conductive semiconductor layer and the active layer into an active region and an inactive region, and the first pad vertically overlaps the

Abstract: The present invention relates to: an indole derivative, which is a novel cell mitosis inhibitor; a stereoisomer thereof or a pharmaceutically acceptable salt thereof; a use thereof as a therapeutic agent; a composition containing the same and a treatment method using the composition; and a preparation method therefor. According to the present invention, the indole derivative, the stereoisomer thereof or the pharmaceutically acceptable salt thereof, inhibits the tubulin polymerization during mitosis so as to induce apoptosis, and has an excellent anti-cancer effect also in cancer cells having multiple drug resistance.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.