Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.

Abstract: A secondary battery activation method includes a pre-aging step for aging, at room temperature, a secondary battery comprising a positive electrode comprising a positive electrode active material, a negative electrode comprising a negative electrode active material, a separator disposed between the positive electrode and the negative electrode, and an electrolyte; a charging step for primarily charging the pre-aged secondary battery to 60% or more of state of charge (SOC) of the secondary battery; a high-temperature aging step for aging the primarily charged secondary battery at a high temperature; and a room-temperature aging step for aging, at room temperature, the secondary battery which has been aged at a high temperature, wherein the high-temperature aging step is performed at a temperature of 60° C. or higher.

Abstract: An embodiment relates to a light emitting device comprise a second electrode which includes indium tin oxide (ITO), an ohmic characteristic between a second semiconductor layer and the second electrode is improved and a driving voltage is also improved. An embodiment relates to a light emitting device comprise a capping layer that can overlap the second semiconductor layer with the second electrode interposed therebetween and include a material of which a difference in thermal expansion coefficient with the second semiconductor layer is 3 or less. Therefore, since the capping layer is electrically connected to the second electrode, delamination and lifting of an interface between the second electrode and the second semiconductor layer is prevented, and reliability of the light emitting device is improved.

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

Abstract: The present invention relates to a photo-cross-linkable shape-memory polymer and a preparation method therefor. The shape-memory polymer according to one embodiment of the present invention comprises a photo-cross-linkable functional group, and thus a shape-memory polymer having a melting point suitable for a physiological or medical application device can be provided. Particularly, a method for preparing the shape-memory polymer, according to one embodiment of the present invention, uses a catalyst for inducing the simultaneous ring-opening polymerization of two monomers (CL, GMA) during synthesis of the shape-memory polymer, thereby enabling the synthesis time of the shape-memory polymer to be reduced, and shape-memory polymers having various melting points can be readily prepared by controlling the introduction amounts of CL and GMA.

Abstract: Disclosed is in the embodiment is a semiconductor device comprising: a first conductive semiconductor layer; a second conductive semiconductor layer; an active layer disposed between the second conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer includes a first sub semiconductor layer, a third sub semiconductor layer and a second sub semiconductor layer disposed between the first sub semiconductor layer and the third sub semiconductor layer, wherein proportion of aluminum in the first sub semiconductor layer and the third sub semiconductor layer is larger than an proportion of aluminum in the active layer, and an proportion of aluminum in the second sub semiconductor layer is smaller than the proportion of aluminum in the first sub semiconductor layer and the

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

Abstract: Some example embodiments include methods of operating a wireless communication device supporting carrier aggregation, the methods include allocating a memory of a plurality of memories to each of a plurality of component carriers based on a memory allocation priority; determining a demodulation priority for each of the plurality of component carriers based on one of a size of each memory allocated to each of the plurality of component carriers, and the memory allocation priority; and demodulating signals received via the plurality of component carriers based on the demodulation priority.

Abstract: Disclosed in an embodiment is a semiconductor device comprising: a semiconductor structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a second electrode electrically connected to the second conductive type semiconductor layer; and a reflective layer disposed under the second electrode, wherein the second conductive type semiconductor layer comprises a first sub-layer and a second sub-layer disposed between the first sub-layer and the active layer and having an aluminum (Al) composition higher than that of the first sub-layer, the reflective layer comes into contact with the lower surface of the second sub-layer, and the second electrode comes into contact with the first sub-layer.

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.

Abstract: A secondary battery charging method that shortens charging time includes a step for introducing a plurality of battery cells onto an activation tray and CC-charging the battery cells; and a step for connecting the plurality of battery cells in parallel. The charging method according to the present invention shortens the time typically required for CV-charging by connecting battery cells in parallel after CC-charging, thus having the effect of replacing CV-charging.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.

Abstract: A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

Abstract: An electrode includes a unit body stack part formed by stacking at least one basic unit having a four-layer structure in which a first electrode, a first separator, a second electrode and a second separator are sequentially stacked. Each surface of the first separator and the second separator is coated with a coating material having adhesiveness, and the basic unit adheres to an adjacent radial unit in the unit body stack part. The electrode assembly of allows a heating and pressing process to be performed prior to a primary formation process so that a separator of one basic unit and a first electrode of the other basic unit to be adhered and fixed by a coating material coated on the separator, and thus a bending phenomenon caused by a difference in electrode expansion rates in a charging/discharging process is prevented.