Patents by Inventor Joseph Bennett

Joseph Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7567913
    Abstract: A method is provided for receiving an order for a laboratory test of a biological specimen for a patient utilizing a computer network including a client computer and a central computer. The method includes facilitating a connection between the client computer and the central computer. A laboratory test request is received at the central computer from the client computer. Patient, billing, and diagnosis information corresponding to the requested laboratory test is also received at the central computer from the client computer. Information is transmitted from the central computer to the client computer for generating a test requisition and a label for use with the biological specimen.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: July 28, 2009
    Assignee: Quest Diagnostics Inc.
    Inventors: Richard Joseph Bennett, Albert A. Tate, David Andrew Rapperport, Ryan Michael Eastman, Randall Scott DeBold
  • Patent number: 7506093
    Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Joseph A. Bennett, David Sastry
  • Publication number: 20090045597
    Abstract: A vehicle includes a deck, an aft running gear attached to the deck, a steering assembly, a flexible joint attaching the steering assembly to the deck, such that the steering assembly is pivotable about the flexible joint with respect to the deck between a rider-standing mode and a rider-sitting mode, and a brake assembly attached to the deck.
    Type: Application
    Filed: March 22, 2007
    Publication date: February 19, 2009
    Inventor: Michael Joseph Bennett
  • Publication number: 20080263250
    Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 23, 2008
    Inventor: Joseph A. Bennett
  • Patent number: 7409483
    Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 5, 2008
    Assignee: Intel Corporation
    Inventor: Joseph A. Bennett
  • Publication number: 20080162976
    Abstract: Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Joseph A. Bennett, Jeffrey R. Wilcox
  • Patent number: 7370215
    Abstract: A system includes a host that may be used to interface with an advanced technology attachment (ATA) device. The host includes at least one timer used to determine when to place the ATA device in a low power mode independently of an operating system (OS).
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventor: Joseph Bennett
  • Publication number: 20080052438
    Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.
    Type: Application
    Filed: March 27, 2007
    Publication date: February 28, 2008
    Inventors: Joseph Bennett, David Sastry
  • Publication number: 20080045299
    Abstract: A system and method for providing an additional or end-of-game drawing to players of a lottery game is provided. In one embodiment, unique validation codes provided on lottery tickets can be encrypted using an algorithm and used to create a record of such encrypted codes. A player then participates in the lottery and subsequently submits the validation code from the ticket to a lottery provider. The lottery provider applies the algorithm to the submitted validation code to create another encryption code for comparison with the record of encrypted codes. In the event a match is found, the player is entered into a second-chance or end of game drawing. Upon entry, the player is no longer required to maintain possession of the ticket for subsequent validation.
    Type: Application
    Filed: August 21, 2007
    Publication date: February 21, 2008
    Inventors: JOSEPH BENNETT, JEFFREY MARTINECK
  • Patent number: 7328300
    Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventor: Joseph A. Bennett
  • Patent number: 7260661
    Abstract: An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine associates a first transaction identifier with the request packet. A receive engine receives a reply packet in response to the request packet. The reply packet contains a second transaction identifier. The receive engine compares the first transaction identifier to the second transaction identifier. If the first transaction identifier matches the second transaction identifier, the receive engine decides to store data from the reply packet at an address associated with the first transaction identifier.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventors: James Bury, Mark Sullivan, Joseph A. Bennett
  • Patent number: 7225326
    Abstract: One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventor: Joseph A. Bennett
  • Publication number: 20070107915
    Abstract: A device for protecting flammable fluid reservoirs, or the regions in immediate proximity thereof, from the hazards due to impact and reservoir rupture, and subsequent potential of fire, corrosion or other damage or injury due to contact with reactive fluids. Such impacts may arise from collisions, such as encountered in transportation systems, or structural or thermal failure and/or rupture of components and systems, or separation of system components. Such a device may be formed as a close-fitting shroud over such components, or surrounding fittings and junctions of mating components in such systems, or mounted near the location of such components in the direction of impact or failure. Such a device may have a pattern of pre-scored lines to facilitate break-up of the device upon impact or thermal stress.
    Type: Application
    Filed: December 1, 2006
    Publication date: May 17, 2007
    Inventor: Joseph Bennett
  • Patent number: 7203785
    Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Joseph A. Bennett, David Sastry
  • Publication number: 20070068686
    Abstract: A hazard control system according to various aspects of the present invention comprises a housing configured to contain a control material and deliver the control material to neutralize a hazard in response to a trigger event. In one embodiment, the control material is an extinguishant for retarding fire. The housing contains the extinguishant and includes at least one surface configured to rupture in response to a trigger event, such as an impact. The housing may also include a surface configured to substantially mate with a surface of a vehicle, such as a fuel tank surface.
    Type: Application
    Filed: June 12, 2006
    Publication date: March 29, 2007
    Inventor: Joseph Bennett
  • Publication number: 20060294403
    Abstract: A system includes a host that may be used to interface with an advanced technology attachment (ATA) device. The host includes at least one timer used to determine when to place the ATA device in a low power mode independently of an operating system (OS).
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventor: Joseph Bennett
  • Publication number: 20060294274
    Abstract: In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetches simultaneously with one or more other controllers of the plurality of controllers. Other embodiments are also described.
    Type: Application
    Filed: June 23, 2005
    Publication date: December 28, 2006
    Inventor: Joseph Bennett
  • Patent number: 7130992
    Abstract: The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: David I. Poisner, Joseph A. Bennett
  • Patent number: 7107369
    Abstract: In processor-based systems, loss of ports may be avoided while connecting mass storage drives or devices at a host level. In one embodiment, a slave device (e.g., a cache or an accelerator) may be interposed between a host device and a master storage device (e.g., a disk drive) over a serialized link, providing accelerated communications between the host device and the master storage device through the slave device both coupled on select one of one or more ports available at the host device for device connections.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Joseph A. Bennett, Knut S. Grimsrud
  • Publication number: 20060120372
    Abstract: Embodiments are generally direct to a method and apparatus to generate a data descriptor. In one embodiment, a data descriptor is generated for a block of data to be forwarded from a node to another node on a communication link. The data descriptor includes an indication to build a data packet containing at least a portion of the block of data in an accelerated or a non-accelerated manner.
    Type: Application
    Filed: December 8, 2004
    Publication date: June 8, 2006
    Inventors: Jim Bury, Joseph Bennett, Mark Sullivan