Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine associates a first transaction identifier with the request packet. A receive engine receives a reply packet in response to the request packet. The reply packet contains a second transaction identifier. The receive engine compares the first transaction identifier to the second transaction identifier. If the first transaction identifier matches the second transaction identifier, the receive engine decides to store data from the reply packet at an address associated with the first transaction identifier.

Abstract: Embodiments are generally direct to a method and apparatus for generating a header in a communication network. In one embodiment, receiving at a node on a first communication link a protocol data unit (PDU), generating a header that is non-specific to a particular communication protocol associated with the PDU when received at the node, the header to facilitate encapsulation and transportation of the PDU through a second communication link to deliver the PDU to a memory-based service interface of another node on the second communication link.

Abstract: An apparatus generates a data packet for an advanced switching (AS) fabric. The apparatus includes a direct memory access (DMA) engine that retrieves a descriptor from a queue, and that stores the descriptor in a storage area. The descriptor contains information used to build the data packet. A work manager retrieves the descriptor from the storage area, and works to generate the data packet using the descriptor.

Abstract: Circuitry is used for generating one or more commands to access a ring buffer on an end node device of an advanced switching (AS) fabric. The circuitry includes circuits to receive information for accessing the ring buffer and to generate a current command based on the information. The information includes an address of the ring buffer and a length of data associated with buffer access. The circuitry also includes a controller to determine whether the information is for one command or for plural commands. If the information is for plural commands, the circuits generate the plural commands by updating the information following generation of the current command and by generating a subsequent command using updated information.

Abstract: In some embodiments, the inventions include a chip having a status register circuit coupled to conductors to receive interrupt event signals to provide source signals corresponding to the interrupt event signals. The chip also includes a control register circuit to provide source enable signals for selective ones of the interrupt sources, and a re-arming logic circuit coupled to the conductors to receive the interrupt event signals and provide a re-arming signal. The chip further includes first logic circuit to receive the source signals, the source enable signals, and the re-arming signal to provide an initial interrupt signal, and message signaled interrupt (MSI) signal pulse generation logic to receive the initial interrupt signal and provide an MSI signal in response thereto. Other embodiments are described and claimed.

Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.

Abstract: One embodiment of a system for disabling a computer bus upon detection of a power fault includes a bus bridge device coupled to a bus and a power regulator that delivers power to the bus. If the power regulator detects a power fault, then the power regulator asserts a fault signal to the bus bridge device. The power regulator also removes power from the bus. The bus bridge device disconnects an internal logic unit from the bus in response to the assertion of the fault signal. The bus bridge device, in further response to the assertion of the fault signal, alerts the system of the power fault by asserting an interrupt signal.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A method and apparatus for suppressing a fire utilizing non-azide solid gas propellant generation to produce and transport a suitable gas for suppressing a fire in a normally occupied area. The nitrogen gas produced by the solid propellant gas generation is optionally treated to remove undesirable elements such as water and/or carbon dioxide from the product gas prior to the delivery of the product gas to the protected hazard area.

Abstract: A method and apparatus for suppressing a fire utilizing non-azide solid gas propellant generation to produce and transport a suitable gas for suppressing a fire in a normally occupied area. The nitrogen gas produced by the solid propellant gas generation is optionally treated to remove undesirable elements such as water and/or carbon dioxide from the product gas prior to the delivery of the product gas to the protected hazard area.

Abstract: In some embodiments, a register is to store one or more bits indicating whether a low power mode is to be entered. A controller is to put at least one link in a low power state in response to the one or more bits indicating whether a low power mode is to be entered without waiting for a software interrupt routine when a particular condition occurs (for example, when the link is idle and/or when there are no commands outstanding and no commands to issue on the link). Other embodiments are described and claimed.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status.

Abstract: One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status.

Abstract: A fire control system according to various aspects of the present invention includes an extinguishant configured to absorb heat from the fire. In one embodiment, the extinguishant is configured to absorb thermal radiation from the fire and inhibit reflection of thermal radiation from the extinguishant and/or other surfaces back into the fire. In additional and alternative embodiments, the extinguishant includes a thermal absorbant may be configured to transfer heat into the surface and/or interior of suppressant particles or droplets to promote activation of the suppressant.

Abstract: The present invention is in the field of bridging transactions from one bus to a second bus. More particularly, embodiments of the present invention can enhance an interface between two buses by ordering split-completion transactions to one or more hosts.