Abstract: The present invention relates to a method and apparatus for restoring a status data in a computer system.

Abstract: An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from a non-legacy Peripheral Component Interconnect (PCI) bus to an external interrupt controller. Such an interrupt routing mechanism may be implemented by a series of logic gates such as OR gates and AND gates for combining all interrupts from a non-legacy PCI bus to produce an output boot interrupt to an external interrupt controller, and alternatively, implemented by a series of AND gates for combining all interrupts from a non-legacy PCI bus and a switch for forwarding an output boot interrupt to an external interrupt controller in accordance with a disable bit used for the steering function.

Abstract: A gross pollutant trap (50) to be installed in a storm water channel so as to receive storm water flowing through the channel and to filer gross pollutants from the storm water. The trap (50) includes a gross pollutant collection area (61) toward which there extends generally parallel sets (63) and (67) of vanes (64) and (68). The area (61) is at least partly defined by a mesh wall (72) through which water returns to the storm water channel.

Abstract: The present invention is a method and system to automatic loading program on a medium into memory for execution. In one embodiment, a mode word is configured. The insertion of the medium into a drive is detected based on the mode word. A program on the medium is started when insertion is detected. In another embodiment, a polling circuit in a chipset detects the insertion of the medium into the drive. A status bit is checked in response to an interrupt generated by the polling circuit. A flag in a memory is updated based on the status bit. A poll request by an operating system is responded.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: A method and apparatus are provided for fetching data from a memory component. Parameters relating to data fetching may be obtained based on an operating frequency of a bus. These parameters may be stored in registers and include an initial request length, an initial threshold length, a subsequent request length, and a subsequent threshold length. Data may be fetched from the memory component based on the obtained parameters.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: One embodiment of a system for disabling a computer bus upon detection of a power fault includes a bus bridge device coupled to a bus and a power regulator that delivers power to the bus. If the power regulator detects a power fault, then the power regulator asserts a fault signal to the bus bridge device. The power regulator also removes power from the bus. The bus bridge device disconnects an internal logic unit from the bus in response to the assertion of the fault signal. The bus bridge device, in further response to the assertion of the fault signal, alerts the system of the power fault by asserting an interrupt signal.

Abstract: This invention provides methods of treating cancer employing mutant herpes viruses and anticancer agents, such as chemotherapeutic drugs.

Abstract: A growth pollutant trap (50) to be installed in a storm water channel so as to receive storm water flowing through the channel and to filter growth pollutants from the storm water. The trap (50) includes a growth pollutant collection area (61) toward which there extends generally parallel sets (63) and (67) of veins (64) and (68). The area (61) is at least partly defined by a mesh wall (72) through which water returns to the storm water channel.

Abstract: The present invention relates to a method and apparatus for restoring a status data in a computer system.

Abstract: The present invention relates to a method and apparatus for restoring a status data in a computer system.

Abstract: The present invention relates to a method and apparatus for directing causes of non-maskable interrupts. The apparatus determines whether a computer system is designed to handle an alternative interrupt such as a SCI interrupt. If the system is capable of handling alternative interrupts, forwarding circuitry forwards the causes of non-maskable interrupts to an alternative interrupt handler. If the system is not capable of handling alternative interrupts, the apparatus forwards the cause of non-maskable interrupts to a NMI handler.

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

Abstract: A method and apparatus which may be used for direct memory access (DMA) acknowledges. A method of acknowledging a request for access to a bus from a bus agent access involves receiving a request for access to the bus and generating a request acknowledge signal. The request acknowledge is generated on a multiplexed bus in response to the request for access to the bus.

Abstract: A system having a bus coupled to a host and a peripheral controller device each coupled to a bus. The bus includes a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device communicates with the host over the bus to control devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers and memory devices.

Abstract: A system including a host, a peripheral controller device, and a bus master device each coupled to a bus having a plurality of general purpose signal lines for carrying time-multiplexed address, data, and control information. The bus master device communicates with the host and the peripheral controller device via the bus.

Abstract: A filter apparatus (10) having an upstream first filter grate (17) to which stormwater is delivered so that litter is filtered therefrom. Litter is delivered to a first litter collection surface (20). Extending upwardly from the surface (20) is a filter wall (22) having a filter portion (31) through which the stormwater again passes to filter litter therefrom. A second filter grate (24) extends from an upper portion of the wall (22), the second grate (24) leading to a second litter collection surface (26).

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

Abstract: A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer.