Abstract: A system and method to determine a port that a codec is attached is disclosed. An access will be attempted to a codec, and the internal hardware of the host will watch which input port the response comes in on, and log that port for the software. Software can then map that input port to direct memory access/addressing engines in the host such that data streams can be steered to the appropriate application.

Abstract: One embodiment involves having a processor write a data transfer command to cacheable system memory. The processor then performs a write transaction to a deliver a “packet” command to an optical storage device. The optical storage device responds to the packet command by issuing an interrupt once the optical storage device has processed the packet command. The issuance of the interrupt indicates that the optical storage device is ready to receive a data transfer command. A host controller that is coupled to the optical storage device via a serial interconnect receives the interrupt. The host controller then causes a DMA transfer to occur which reads the data transfer command located in system memory and delivers the data transfer command to the optical storage device. The processor is not involved in servicing the interrupt and is therefore freed up to perform other tasks and overall system performance is improved.

Abstract: A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Abstract: One embodiment involves having a processor writing disk drive command information to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The host controller then causes a DMA transfer to occur which reads the command information located in system memory. Once the host controller has the command information, it programs the disk drive over an interconnect. Because the processor can write to cacheable system memory space much quicker than it can perform non-cacheable memory writes to the host controller or programmed I/O writes to the disk drive, the processor is freed up to perform other tasks and overall system performance is improved.

Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

Abstract: One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status.

Abstract: One embodiment involves having a processor write a data transfer command to cacheable system memory. The processor then performs a write transaction to a deliver a “packet” command to an optical storage device. The optical storage device responds to the packet command by issuing an interrupt once the optical storage device has processed the packet command. The issuance of the interrupt indicates that the optical storage device is ready to receive a data transfer command. A host controller that is coupled to the optical storage device via a serial interconnect receives the interrupt. The host controller then causes a DMA transfer to occur which reads the data transfer command located in system memory and delivers the data transfer command to the optical storage device. The processor is not involved in servicing the interrupt and is therefore freed up to perform other tasks and overall system performance is improved.

Abstract: In processor-based systems, loss of ports may be avoided while connecting mass storage drives or devices at a host level. In one embodiment, a slave device (e.g., a cache or an accelerator) may be interposed between a host device and a master storage device (e.g., a disk drive) over a serialized link, providing accelerated communications between the host device and the master storage device through the slave device both coupled on select one of one or more ports available at the host device for device connections.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O) controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: A round robin bus arbitrator that prevents bus starvation caused by an inbound buffer becoming full and forcing repetitive retries by an agent. The arbitrator performs a rotating scan of the request lines of multiple potential bus requesters. When a request is detected, the arbitrator stops, grants the request, and resumes scanning after the requester takes control of the bus. If the data buffer on a write operation becomes full and cannot accept any more data, a signal so indicating is sent to the arbitrator. The arbitrator then stops scanning, or refuses to resume scanning if it is already stopped, until the buffer indicates it is no longer full. The next requester that is granted the bus is therefore not confronted with a full buffer, and not thereby forced to abort the request and make a retry. The invention avoids bus starvation caused by a second bus requestor repeatedly being given a retry response because the buffer is repeatedly filled up by an earlier bus requestor.

Abstract: This invention provides methods of treating cancer employing mutant herpes viruses and anticancer agents, such as chemotherapeutic drugs.

Abstract: Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: A system and method to determine a port that a codec is attached is disclosed. An access will be attempted to a codec, and the internal hardware of the host will watch which input port the response comes in on, and log that port for the software. Software can then map that input port to direct memory access/addressing engines in the host such that data streams can be steered to the appropriate application.

Abstract: A fish hook is provided which includes an elongated shank having a first attaching end and a second end. A locking bend shoulder extends at an angle from the second end of the shank. A weight is secured to the shank between the first attached end and the second end of the shank. The weight is located at a distance from the locking bend shoulder so that the bait is capable of being secured on the shank. The fish hook has a curved section terminating in a barb section. The barb section of the hook is axially aligned with the shank so that the bait is properly balanced on the hook when secured to the shank and the barb section.

Abstract: A data fetching control mechanism of a host chipset is disclosed for determining a fetch size to fetch data from a memory subsystem of a computer system. Such a data fetching control mechanism comprises input logics coupled to receive variables of a read command, a bus frequency, a bus data width from a bus device; and an index table which generates fetch values indicating fetch sizes of data to be fetched from a memory subsystem on one side of a host chipset, via a primary bus, for the bus device on the other side of the host chipset, via a secondary bus.

Abstract: The present invention is in the field of bridging transactions from one bus to a second bus. More particularly, embodiments of the present invention can enhance an interface between two buses by ordering split-completion transactions to one or more hosts.

Abstract: A method is provided for receiving an order for a laboratory test of a biological specimen for a patient utilizing a computer network including a client computer and a central computer. The method includes facilitating a connection between the client computer and the central computer. A laboratory test request is received at the central computer from the client computer. Patient, billing, and diagnosis information corresponding to the requested laboratory test is also received at the central computer from the client computer. Information is transmitted from the central computer to the client computer for generating a test requisition and a label for use with the biological specimen.