Patents by Inventor Joshua D. Heppner

Joshua D. Heppner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10056182
    Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Gregorio R. Murtagian, Robert L. Sankman, Brent S. Stone, Kaladhar Radhakrishnan, Joshua D. Heppner
  • Publication number: 20180226358
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 9, 2018
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20180166363
    Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.
    Type: Application
    Filed: April 1, 2016
    Publication date: June 14, 2018
    Inventors: Joshua D. Heppner, Mitul B. Modi
  • Patent number: 9953929
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Patent number: 9953909
    Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Zuyang Liang, Michael Garcia, Joshua D. Heppner, Srikant Nekkanty
  • Publication number: 20180096862
    Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 5, 2018
    Inventors: Sasha N. Oster, Adel A. Elsherbini, Joshua D. Heppner, Shawna M. Liff
  • Publication number: 20180061673
    Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.
    Type: Application
    Filed: August 7, 2017
    Publication date: March 1, 2018
    Applicant: INTEL CORPORATION
    Inventors: JOSHUA D. HEPPNER, SERGE ROUX, MICHAEL J. BAKER, JAVIER A. FALCON
  • Publication number: 20180019193
    Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Inventors: Zuyang Liang, Michael Garcia, Joshua D. Heppner, Srikant Nekkanty
  • Publication number: 20180019558
    Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 18, 2018
    Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
  • Patent number: 9824901
    Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Adel A. Elsherbini, Joshua D. Heppner, Shawna M. Liff
  • Patent number: 9795026
    Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Nayandeep K. Mahanta, Joshua D. Heppner, Adel A. Elsherbini
  • Publication number: 20170287771
    Abstract: A substrate retention plate system for holding a substrate for processing in an electronic device manufacturing process is described. The retention plate system includes a top plate and a bottom plate to sandwich a flexible substrate. Additionally, the top plate includes a number of cams to stretch the flexible substrate across the bottom plate.
    Type: Application
    Filed: April 2, 2016
    Publication date: October 5, 2017
    Applicant: INTEL CORPORATION
    Inventors: DANIEL CHAVEZ-CLEMENTE, JOSHUA D. HEPPNER, NAIDA DURANOVIC
  • Publication number: 20170287736
    Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Sasha Oster, Adel A. Elsherbini, Joshua D. Heppner, Shawna M. Liff
  • Publication number: 20170287847
    Abstract: Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Rajendra C. Dias, Robert L. Sankman, Joshua D. Heppner, Mitul B. Modi, Yoshihiro Tomita
  • Patent number: 9780510
    Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Dhanya Athreya, Gaurav Chawla, Kemal Aygun, Glen P. Gordon, Sarah M. Canny, Jeffory L. Smalley, Srikant Nekkanty, Michael Garcia, Joshua D. Heppner
  • Publication number: 20170266948
    Abstract: Described is an apparatus which comprises: a squeegee head which is operable to drop a material; and a vacuum manifold attachable to the squeegee head, wherein the vacuum manifold is operable to create a vacuum in a space prior to the squeegee head is to drop the material.
    Type: Application
    Filed: March 16, 2016
    Publication date: September 21, 2017
    Inventors: Joshua D. Heppner, Shawna M. Liff, Eric J. Li, Anna M. Prakash
  • Publication number: 20170271270
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20170250145
    Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Rajendra C. Dias, Joshua D. Heppner, Mitul B. Modi, Anna M. Prakash
  • Patent number: 9728425
    Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Joshua D. Heppner, Serge Roux, Michael J. Baker, Javier A. Falcon
  • Patent number: 9704811
    Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Joshua D Heppner, Mitul B Modi, Anna M. Prakash