Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: An active pixel sensor (APS) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein. The vertical transfer gate extends into the semiconductor substrate with a channel region in electrical communication with the photodetector. The pixel transistor is arranged over the photodetector and configured to facilitate the pixel operation (e.g., reset, signal readout, etc.). The implant isolation region is arranged in the semiconductor substrate and surrounds and electrically isolates the pixel transistor. A method for manufacturing the APS is also provided.

Abstract: A surveillance method is utilized in a camera system, wherein the camera system comprises a display device, a controller, a first camera disposed fixedly on a base of the camera system and constantly facing toward a first direction, and at least a second camera disposed on the base and controlled by the controller to rotate around the first camera. The surveillance method comprises the display device displaying a wide-angle image captured by the first camera; the controller receiving at least a directional instruction corresponding to at least a specific part of the wide-angle image; and the controller generating a plurality of control signals to steer the at least a second camera toward at least a second direction according to the at least a directional instruction.

Abstract: The present disclosure discloses an electrical connector and a plug-in module. The plug-in module includes a base, a plurality of input terminals, a plurality of output terminals and a PCB module. The base includes a bottom plate, a front plate and a back plate, and a tongue plate extending from the bottom plate forward beyond the front plate; the plurality of input terminals are fixed to the back plate, and two ends of each of the input terminals extend respectively beyond a top end of the back plate and a bottom end of the bottom plate; the plurality of output terminals are fixed to the tongue plate and the front plate, and two ends of each of the output terminals extend respectively beyond a top end of the front plate and the tongue plate; and the PCB module includes at least one circuit board.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A wrench quick release apparatus includes a sleeve, a positioning unit, a wrench unit and an elasticity unit. The sleeve includes a channel and an engaging section for engaging to a first plate. The positioning unit inserts in the channel of the sleeve, and includes one end inserted through the first plate and an opposite end protrudes out from the channel of the sleeve. The wrench unit is pivotally connected to the positioning unit and protrudes out from one end of the sleeve. The elasticity unit includes one end pushed against the positioning unit and an opposite end pushed against the sleeve. Accordingly, the wrench quick release apparatus is first engaged to the first plate through the sleeve and then engaged to or disengaged from a second plate.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.

Abstract: An electric connector, a plug-in module thereof and a production method of the plug-in module are provided. The plug-in module comprises a base, an input unit, an output unit and an output end. The base comprises a top plate, a bottom plate and one connection plate. A plurality of input terminals and a plurality of intermediate terminals are fixed to the base. The input unit comprises one input circuit board provided vertically to the base and electrically coupled to an end portion of the input terminals. At least one channel are provided on the input circuit board. Each channel comprises a transformer electrically coupled to the input circuit board. The output unit comprises an output circuit board horizontally provided to the base and electrically coupled to the input circuit board via the intermediate terminals. The output end are fixed to and electrically coupled to the output circuit board.

Abstract: An end effector controlling method includes the steps of obtaining the 3D physical information of an object, finding an appropriate sucking position by a vector programming method, generating a control command to control the sucking position of an end effector. The vector programming method includes the steps of creating a virtual platform and creating a virtual object on the virtual platform from the obtained 3D physical information, obtaining reference planes from each reference axis, computing a curve of surface interactions of each reference plane and the virtual object separately, and searching a sucking position on each curve according to a reachable range of a finger. of the end effector.

Abstract: A quick release connecting device includes an actuating retainer having an internal receiving space, at least one first push section and a retaining section for detachably engaging with a first object; a fixing member including a body portion movably associated with the receiving space and a pivot portion formed on the body portion for detachably connecting with a second object; pin connection means connecting the body portion to the receiving space for the actuating retainer and the fixing member to move relative to each other within a limited range; an elastic element having two ends pressed against an inner wall surface of the receiving space and the body portion to control the limited movement of the actuating retainer and the fixing member and return them to their original positions. With the quick release connecting device, two mating objects can be conveniently repeatedly connected to and separated from each other.

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract: A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected from the group consisting essentially of a reset transistor, a selector, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit.

Abstract: A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a color filter layer over the photo conversion layer, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filter layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer, wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second pixel.

Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.

Abstract: A space-saving resilient assembly element is adapted to fix a first object and a second object in place. The resilient assembly element includes an assembly element body and a conical resilient element. The assembly element body has a head, a rod connected to the head, and an assembly portion connected to the rod. The assembly portion connects with the first object. The conical resilient element is disposed around the rod. The conical resilient element has a first end and a second end. The first end abuts against the head, and the second end abuts against the second object. The conical resilient element is compressed and deformed to become tablet-shaped, curved, conical, or layer by layer. Therefore, the space occupied by the resilient assembly element is reduced.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor and a method for fabricating the same are provided. An example CMOS image sensor includes first active regions of a semiconductor substrate, where the first active regions are arranged in rows or columns. Photosensitive regions are formed in the first active regions. The CMOS image sensor also includes second active regions of the semiconductor substrate that are interposed between the first active regions. Each of the second active regions includes a device isolation region formed by doping the semiconductor substrate with impurities. Each of the second active regions also includes a channel region of a field effect transistor (FET) that is formed within the device isolation region and is configured to connect source and drain regions of the FET. At least one control gate is formed over each of the second active regions.

Abstract: A method for forming a photo diode is provided. The method includes: forming a first bottom electrode corresponding to a first pixel and a second bottom electrode corresponding to a second pixel over a substrate; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a top electrode over the photo conversion layer; forming a color filter layer over the top electrode, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer.