Patents by Inventor Julien Frougier

Julien Frougier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

SEMICONDUCTOR STRUCTURES WITH POWER RAIL DISPOSED UNDER ACTIVE GATE

Publication number: 20230087690

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.

Type: Application

Filed: September 20, 2021

Publication date: March 23, 2023

Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
BACKSIDE ELECTRICAL CONTACTS TO BURIED POWER RAILS

Publication number: 20230093101

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Type: Application

Filed: September 22, 2021

Publication date: March 23, 2023

Inventors: Ruilong XIE, Brent ANDERSON, Albert M. YOUNG, Kangguo CHENG, Julien FROUGIER, Balasubramanian PRANATHARTHIHARAN, Roy R. YU, Takeshi NOGAMI
SEMICONDUCTOR STRUCTURES WITH BACKSIDE GATE CONTACTS

Publication number: 20230086033

Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

Type: Application

Filed: September 21, 2021

Publication date: March 23, 2023

Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet, Dechao Guo, Kisik Choi, Kangguo Cheng, Carl Radens
Stacked FET with Independent Gate Control

Publication number: 20230090346

Abstract: Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.

Type: Application

Filed: September 23, 2021

Publication date: March 23, 2023

Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, JUNTAO LI, CHANRO PARK
BURIED POWER RAIL FOR SEMICONDUCTORS

Publication number: 20230083432

Abstract: A semiconductor structure includes a field effect transistor (FET) having a source/drain, a contact in contact with the source/drain, and a buried power rail including a conductive material, wherein the buried power rail is in contact with the contact, wherein a first portion of the buried power rail closest to the contact has a first thickness, and wherein a second portion of the buried power rail has a second thickness such that the first thickness is less than the second thickness.

Type: Application

Filed: September 14, 2021

Publication date: March 16, 2023

Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
INTEGRATED NANOSHEET FIELD EFFECT TRANSISTORS AND FLOATING GATE MEMORY CELLS

Publication number: 20230085033

Abstract: A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.

Type: Application

Filed: September 13, 2021

Publication date: March 16, 2023

Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek
MTJ-based analog memory device

Patent number: 11605409

Abstract: A magnetic domain device is provided in which a magnetic free layer (i.e., the storage layer) of a magnetic tunnel junction (MTJ) pillar is in close proximity to a conductive write line that is disposed beneath the MTJ pillar. The magnetic domain device further includes a pair of spaced apart bottom electrodes located beneath the conductive write line, and a top electrode located on the MTJ pillar. The magnetic domain device can be used in analog memories including multi-bit storage, analog memory for artificial intelligence (AI) applications.

Type: Grant

Filed: October 27, 2020

Date of Patent: March 14, 2023

Assignee: International Business Machines Corporation

Inventors: Dimitri Houssameddine, Julien Frougier, Kangguo Cheng, Ruilong Xie
Steep-switch field effect transistor with integrated bi-stable resistive system

Patent number: 11605672

Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.

Type: Grant

Filed: December 21, 2020

Date of Patent: March 14, 2023

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
COMPACT MRAM ARCHITECTURE WITH MAGNETIC BOTTOM ELECTRODE

Publication number: 20230074676

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode u can be made a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

Type: Application

Filed: September 8, 2021

Publication date: March 9, 2023

Inventors: Julien Frougier, Karthik Yogendra, Dimitri Houssameddine, Kangguo Cheng, Ruilong Xie
PHASE CHANGE MEMORY WITH HEATER

Publication number: 20230074555

Abstract: A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.

Type: Application

Filed: August 25, 2021

Publication date: March 9, 2023

Inventors: Kangguo Cheng, CHANRO PARK, Julien Frougier, Ruilong Xie
AIRGAP GATE SPACER

Publication number: 20230077243

Abstract: A semiconductor device includes a gate structure that is formed upon and around a channel fin. The device further includes a source or drain (S/D) region connected to the fin. A spacer liner is located upon a sidewall of the S/D region facing the gate structure. An air-gap spacer is located between the gate structure and the spacer liner. A spacer ear is located above the air-gap spacer between the gate structure and the spacer liner. The spacer ear may be formed by initially forming an inner spacer upon a sidewall of the gate structure and forming an outer spacer upon the inner spacer. The outer spacer may be recessed below the inner spacer and the spacer ear may be formed upon the recessed outer spacer. Subsequently, the inner spacer and outer spacer may be removed to form the air-gap spacer while retaining the spacer ear.

Type: Application

Filed: September 7, 2021

Publication date: March 9, 2023

Inventors: Ruilong Xie, Kangguo Cheng, Julien Frougier, Chanro Park
SELF-ALIGNED BURIED POWER RAIL CAP FOR SEMICONDUCTOR DEVICES

Publication number: 20230073924

Abstract: A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.

Type: Application

Filed: September 3, 2021

Publication date: March 9, 2023

Inventors: Ruilong Xie, HUIMEI ZHOU, Julien Frougier, Kisik Choi
STRAIN GENERATION AND ANCHORING IN GATE-ALL-AROUND FIELD EFFECT TRANSISTORS

Publication number: 20230065970

Abstract: Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Type: Application

Filed: August 31, 2021

Publication date: March 2, 2023

Inventors: Julien Frougier, Sung Dae Suk, Kangguo Cheng, Andrew M. Greene, Ruilong Xie
NANOSHEET-BASED SEMICONDUCTOR STRUCTURE WITH DIELECTRIC PILLAR

Publication number: 20230066597

Abstract: A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.

Type: Application

Filed: August 31, 2021

Publication date: March 2, 2023

Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
MRAM STACK WITH REDUCED HEIGHT

Publication number: 20230060906

Abstract: A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.

Type: Application

Filed: September 1, 2021

Publication date: March 2, 2023

Inventors: Ruilong Xie, Dimitri Houssameddine, Kangguo Cheng, Julien Frougier, Bruce B. Doris
CONDUCTIVE-BRIDGING SEMICONDUCTOR MEMORY DEVICE FORMED BY SELECTIVE DEPOSITION

Publication number: 20230068851

Abstract: A memory cell and formation thereof. The memory cell including: a first dielectric material having a via; a dielectric spacer on a sidewall of the via, and a second dielectric material pinching off the via and forming a seam.

Type: Application

Filed: August 30, 2021

Publication date: March 2, 2023

Inventors: Kangguo Cheng, Chanro Park, Julien Frougier, Ruilong Xie
FORMING DIELECTRIC SIDEWALL AND BOTTOM DIELECTRIC ISOLATION IN FORK-FET DEVICES

Publication number: 20230066979

Abstract: A semiconductor apparatus includes a substrate; a central vertical pillar of dielectric material protruding upward from the substrate; a left plurality of semiconductor fins protruding horizontally from a left side of the central vertical pillar above the substrate; a right plurality of semiconductor fins protruding horizontally from a right side of the central vertical pillar opposite the left plurality of semiconductor fins; a gate stack surrounding the central vertical pillar and the left and right pluralities of semiconductor fins; and a bottom dielectric insulating layer protruding horizontally left and right of the central vertical pillar below the left and right pluralities of fins and adjacent to the substrate.

Type: Application

Filed: August 31, 2021

Publication date: March 2, 2023

Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Dimitri Houssameddine
FIELD EFFECT TRANSISTORS WITH BOTTOM DIELECTRIC ISOLATION

Publication number: 20230060619

Abstract: A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

Type: Application

Filed: August 25, 2021

Publication date: March 2, 2023

Inventors: Julien Frougier, Ruilong Xie, Andrew M. Greene, Veeraraghavan S. Basker
Optimized Contact Resistance for Stacked FET Devices

Publication number: 20230054540

Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.

Type: Application

Filed: August 17, 2021

Publication date: February 23, 2023

Inventors: Ruilong Xie, Heng Wu, Jingyun Zhang, Julien Frougier
DUAL DIELECTRIC PILLAR FORK SHEET DEVICE

Publication number: 20230038116

Abstract: A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.

Type: Application

Filed: August 9, 2021

Publication date: February 9, 2023

Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Dimitri Houssameddine

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