Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.

Abstract: Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

Abstract: A method including forming a plurality of nanosheets on a substrate and forming a plurality of sacrificial layers on the substrate, wherein the plurality of nanosheets and the plurality of sacrificial layers are arranged as alternating layers. Forming and patterning a first hardmask located on top of one of the sacrificial layers and forming a second hardmask around the first hardmask. Patterning the plurality of nanosheets and the plurality of sacrificial layers. Forming and patterning a dummy gate located on top of first hard mask. Removing the plurality of sacrificial layers. Forming a plurality of nanowires, where the plurality of nanowires is formed by the removal of the plurality of sacrificial layers, where the removal of the plurality of sacrificial layers thins sections of each of the plurality of nanowires forming the plurality of nanowires.

Abstract: A semiconductor device is presented that includes source/drain epitaxial regions disposed over a substrate, source/drain contacts (CA) disposed in direct contact with the source/drain epitaxial regions, where at least one of the CA contacts directly contacts a buried power rail or backside power rail through a via-to-BPR (VBPR) contact, a dielectric cap disposed over one or more of the CA contacts, and a local interconnect constructed in direct contact with one area of the dielectric cap such that a portion of the local interconnect is vertically aligned with the backside power rail. A backside power distribution network (BSPDN) is disposed adjacent the backside power rail.

Abstract: A semiconductor device is provided. The semiconductor device includes a protective liner, and a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail. The semiconductor device further includes a source/drain on a second portion of the protective liner, wherein the source/drain is offset from the buried power rail, and a source/drain contact on the source/drain and in electrical communication with the buried power rail.

Abstract: A semiconductor FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region and a common metal contact for the first source/drain region and the second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

Abstract: Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Abstract: A semiconductor device includes a substrate, a first shallow trench isolation (STI) liner disposed above and in contact with the substrate, a bottom dielectric isolation (BDI) region disposed above the substate and in contact with the STI liner, a device channel disposed above the BDI region, and a gate stack disposed above and in contact with the device channel.

Abstract: A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Abstract: An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.

Abstract: A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.

Abstract: A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.

Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

Abstract: A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.

Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Abstract: A semiconductor structure is provided. The semiconductor device includes a magnetic layer located between a first electrode and a second electrode formed on a substrate. The semiconductor device further includes a first write element electrically coupled to the magnetic layer adjacent to the first electrode. The semiconductor device also includes a second write element electrically coupled to the magnetic layer adjacent to the second electrode. The semiconductor device additionally includes a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element.

Abstract: A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.

Abstract: Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a dielectric liner that wraps around a top and one side of a substrate island. The dielectric liner separates a substrate from a gate stack. Further, the system includes an access trench in physical contact with the dielectric liner.