Patents by Inventor Julien Frougier

Julien Frougier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-level ferroelectric memory cell
    Patent number: 11621269
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 4, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Julien Frougier, Ruilong Xie
  • FORK SHEET DEVICE WITH BETTER ELECTROSTATIC CONTROL
    Publication number: 20230095140
    Abstract: A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 30, 2023
    Inventors: Ruilong Xie, Kangguo Cheng, Julien Frougier, CHANRO PARK
  • NANOSHEET TRANSISTORS WITH SELF-ALIGNED GATE CUT
    Publication number: 20230099643
    Abstract: Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Julien Frougier, Huimei Zhou, Ruilong Xie, Chanro Park, Kangguo Cheng
  • NANOSHEET TRANSISTOR WITH ASYMMETRIC JUNCTION AND ROBUST STRUCTURE STABILITY
    Publication number: 20230095447
    Abstract: A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, CHANRO PARK
  • NANOSHEET TRANSISTORS WITH BURIED POWER RAILS
    Publication number: 20230094466
    Abstract: A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Julien Frougier, Nicolas Loubet, Sagarika Mukesh, PRASAD BHOSALE, Ruilong Xie, Andrew Herbert Simon, Takeshi Nogami, Lawrence A. Clevenger, Roy R. Yu, Andrew M. Greene, Daniel Charles Edelstein
  • PLANAR DEVICES WITH CONSISTENT BASE DIELECTRIC
    Publication number: 20230102261
    Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Huimei Zhou, Andrew M. Greene, Julien Frougier, Ruqiang Bao, Jingyun Zhang, Miaomiao Wang, Dechao Guo
  • EMBEDDED MRAM INTEGRATED WITH SUPER VIA AND DUMMY FILL
    Publication number: 20230098033
    Abstract: A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Ruilong Xie, Kangguo Cheng, Dimitri Houssameddine, Julien Frougier
  • SEMICONDUCTOR STRUCTURE HAVING BOTTOM ISOLATION AND ENHANCED CARRIER MOBILITY
    Publication number: 20230086633
    Abstract: Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park, Juntao Li
  • SPIN ORBIT-TORQUE MAGNETIC RANDOM-ACCESS MEMORY (SOT-MRAM) WITH CROSS-POINT SPIN HALL EFFECT (SHE) WRITE LINES AND REMOTE SENSING READ MAGNETIC TUNNEL-JUNCTION (MTJ)
    Publication number: 20230086181
    Abstract: A cross-point SOT-MRAM cell includes: a first SHE write line; a second SHE write line non-colinear to the first SHE write line; a cross-point free layer comprising a first free layer, a second free layer, and a dielectric layer disposed between the first and the second free layers, the cross-point free layer configured to store a magnetic bit and located between and in contact with both the first SHE write line and the second SHE write line; and a remote sensing MTJ located in a vicinity of the cross-point free layer, wherein a free layer sensor of the remote sensing MTJ is in contact with one of the first SHE write line and the second SHE write line.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Julien Frougier, Dimitri Houssameddine, Ruilong Xie, Kangguo Cheng, Michael Rizzolo
  • STACKED PLANAR FIELD EFFECT TRANSISTORS WITH 2D MATERIAL CHANNELS
    Publication number: 20230093343
    Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
  • INCREASED GATE LENGTH AT GIVEN FOOTPRINT FOR NANOSHEET DEVICE
    Publication number: 20230093025
    Abstract: Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, CHANRO PARK
  • METAL GATE N/P BOUNDARY CONTROL BY ACTIVE GATE CUT AND RECESS
    Publication number: 20230086785
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Andrew Gaul, CHANRO PARK, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
  • SEMICONDUCTOR STRUCTURES WITH POWER RAIL DISPOSED UNDER ACTIVE GATE
    Publication number: 20230087690
    Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • BACKSIDE ELECTRICAL CONTACTS TO BURIED POWER RAILS
    Publication number: 20230093101
    Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong XIE, Brent ANDERSON, Albert M. YOUNG, Kangguo CHENG, Julien FROUGIER, Balasubramanian PRANATHARTHIHARAN, Roy R. YU, Takeshi NOGAMI
  • SEMICONDUCTOR STRUCTURES WITH BACKSIDE GATE CONTACTS
    Publication number: 20230086033
    Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet, Dechao Guo, Kisik Choi, Kangguo Cheng, Carl Radens
  • Stacked FET with Independent Gate Control
    Publication number: 20230090346
    Abstract: Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, JUNTAO LI, CHANRO PARK
  • BURIED POWER RAIL FOR SEMICONDUCTORS
    Publication number: 20230083432
    Abstract: A semiconductor structure includes a field effect transistor (FET) having a source/drain, a contact in contact with the source/drain, and a buried power rail including a conductive material, wherein the buried power rail is in contact with the contact, wherein a first portion of the buried power rail closest to the contact has a first thickness, and wherein a second portion of the buried power rail has a second thickness such that the first thickness is less than the second thickness.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Kangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
  • INTEGRATED NANOSHEET FIELD EFFECT TRANSISTORS AND FLOATING GATE MEMORY CELLS
    Publication number: 20230085033
    Abstract: A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek
  • MTJ-based analog memory device
    Patent number: 11605409
    Abstract: A magnetic domain device is provided in which a magnetic free layer (i.e., the storage layer) of a magnetic tunnel junction (MTJ) pillar is in close proximity to a conductive write line that is disposed beneath the MTJ pillar. The magnetic domain device further includes a pair of spaced apart bottom electrodes located beneath the conductive write line, and a top electrode located on the MTJ pillar. The magnetic domain device can be used in analog memories including multi-bit storage, analog memory for artificial intelligence (AI) applications.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Dimitri Houssameddine, Julien Frougier, Kangguo Cheng, Ruilong Xie
  • Steep-switch field effect transistor with integrated bi-stable resistive system
    Patent number: 11605672
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng