Abstract: The present disclosure describes techniques of storing and accessing multimedia files. The techniques comprise obtaining at least two multimedia files; performing format parsing for each of the at least two multimedia files separately to obtain audio encoding data, video encoding data, and container format data of each of the at least two multimedia files; storing the container format data of each of the at least two multimedia files separately, and storing one copy of the audio encoding data and video encoding data; and generating and storing index data comprising information of identifying encoding offset of the container format data, the audio encoding data, and the video encoding data in each of the at least two multimedia files, and comprising information indicative of storage address of the container format data, the audio encoding data, and the video encoding data of each of the at least two multimedia files.

Abstract: Provided are tuning circuit and communication device. The tuning circuit includes tuning switch, ground patch point, and at least two sets of patch units. Each set of patch units at least includes a first patch point and a second patch point; the tuning switch comprises a standard port and at least one conversion port, and each set of patch units is connected to the corresponding conversion port; a first end of a first patch point and a first end of a second patch point in the same set of patch units are connected to the same conversion port; second ends of first patch points in different patch units are respectively connected to different contact points of an antenna; the second ends of all the second patch points are connected to the ground; and both ends of the ground patch point are respectively connected to the standard port and the ground.

Abstract: The present disclosure provides use of lysophosphatidic acid (LPA) as a feed additive in controlling porcine infectious diarrhea, and belongs to the technical field of feed nutrition. The LPA is a type of lipid substance that is produced endogenously in vivo and can reduce a large secretion level of intestinal fluid in piglets caused by Escherichia coli infection via inhibiting cystic fibrosis transmembrane-conductance regulator (CFTR)-dependent iodine efflux. In this way, a susceptibility of weaned piglets to the Escherichia coli is prevented to effectively maintain the intestinal health of piglets. LPA is an endogenous substance in vivo, and it is first discovered that adding the LPA into a feed can control Escherichia coli-caused infectious diarrhea in the piglets.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes: a base plate, configured to place a package chip to be injection-moulded, the package chip including a substrate and at least one chip fixed on a surface of the substrate by a flip chip process, the substrate having a through hole, a glue injection channel being formed in the base plate and configured to inject a moulding compound, and the glue injection channel being connected with the through hole on the substrate. The above-mentioned injection mould can improve the reliability of the package chip after injection moulding.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a metal line over a first substrate, a second substrate over the metal line, and a through-via penetrating through the second substrate and landing on the metal line. The through-via includes a copper fill having at least 85% (111) crystal orientation. The through-via includes a top portion with a first top width over a bottom portion with a second top width that is smaller than the first top width, and the top portion includes a first bulk portion over a first footing feature. The first bulk portion has first sidewalls, the first footing feature has second sidewalls, and the second sidewalls slant inwards from the first sidewalls to narrow the through-via from the first top width of the top portion to the second top width of the bottom portion.

Abstract: A method includes receiving a first wafer having a first device layer on a first semiconductor substrate, receiving a second wafer having a second device layer on a second semiconductor substrate, forming a first groove along a first scribing channel of the first wafer with a non-mechanical cutting process, and forming a second groove along a second scribing channel of the second wafer with the non-mechanical cutting process. The method further includes after the forming of the first and second grooves, bonding the first and second wafers together, and dicing the bonded first and second wafers through the first and second grooves with a mechanical cutting process.

Abstract: One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.

Abstract: The disclosure relates to a method, apparatus, system, medium and electronic device for graph neural network generation. The method includes: obtaining a subgraph structure, the subgraph structure being configured to reflect a graph structure of a corresponding subgraph, and the subgraph comprising a plurality of nodes and edges between the plurality of nodes; obtaining, based on the subgraph structure and according to a predetermined priority, node features of the plurality of nodes and edge features of the edges from a plurality of memories; the predetermined priority being obtained by sorting the plurality of memories in accordance with memory size in an ascending order; fusing, based on the subgraph structure, the node features of the plurality of nodes and the edge features of the edges to obtain subgraph data; and training, based on the subgraph data, the graph neural network.

Abstract: The present disclosure relates to the preparation of a highly pure cannabidiol compound by a novel synthesis route. The cannabidiol compound can be prepared by an acid-catalyzed reaction of a di-halo olivetol with menthadienol, followed by two crystallization steps. The highly pure cannabidiol compound is produced in high yield, stereospecificity, or both, and shows exceedingly low levels of ?-9-tetrahydrocannabinol at the time of preparation and after storage.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: Providing Quality of Service (QOS) for replicating datasets including: receiving, by a target data repository from a source data repository, a checkpoint describing one or more updates to one or more datasets stored in the source data repository and the target data repository; adding, by the target data repository, the checkpoint to a first queue for checkpoints directed to one or more volumes in the target data repository, wherein the first queue is included in a plurality of queues for the target data repository; selecting, by the target data repository, one or more queues from the plurality of queues; and servicing an operation from each of the selected one or more queues.

Abstract: A semiconductor device with a multi-tier construction includes a first tier having a first die, a second die spaced apart from the first die in a first direction and a fill material therebetween. A second tier overlays the first tier, and includes a bridge die partially overlaying the fill material and the first and second dies. The bridge die provides an electrical interconnection between the first and second dies in the first tier. The device also has a first protective structure aligned with a first interface between an end of the first die and the fill material that includes a first part formed on a first side of the first die at the end of the first die; and a second part formed on a first side of the bridge die. The first and second parts are aligned and form the first protective structure, mitigating cracking near the bridge die.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.

Abstract: Provided are balun circuit structure and balun device, the balun circuit structure comprises unbalanced terminal, first and second balanced terminals, grounded power terminal, first, second, third and fourth inductors. The first terminal of the first inductor is connected to the first terminal of the second inductor, the second terminal of the first inductor is connected to the unbalanced terminal, the second terminal of the second inductor is open-circuited, the first terminal of the third inductor and the first terminal of the fourth inductor are connected to the grounded power terminal, the second terminal of the third inductor is connected to the first balanced terminal, the second terminal of the fourth inductor is connected to the second balanced terminal, the first, second, third and fourth inductors are located in different planes, respectively, the first inductor is coupled to the third inductor, and the second inductor is coupled to the fourth inductor.

Abstract: Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.

Abstract: A stiffening girder erection method of a ground-anchored suspension bridge is provided. Clips for all hanger rods of a space main cable suspension bridge are installed such that design center lines of the clips are located in a vertical plane. A first stiffening girder section is installed at a position away from a first tower at a preset distance in a longitudinal direction. A second stiffening girder section is installed at a position away from a second tower at the preset distance along the longitudinal direction. A plurality of third stiffening girder sections are installed one by one in a direction respectively from the first stiffening girder and the second stiffening girder toward a mid-span until a mid-span closure is completed. An azimuth angle of a main cable around a central axis thereof at each of the clips is measured.

Abstract: The present disclosure describes techniques of processing video. The techniques comprise obtaining a video to be transcoded, the video comprising a plurality of frames; setting a test object in each of the plurality of frames of the video to be transcoded; transcoding the video using a predetermined video transcoding mechanism and obtaining the transcoded video; extracting a test object from each of a plurality of frames of the transcoded video; and determining a transcoding result based at least in part on the test object extracted from each of the plurality of frames of the transcoded video.

Abstract: Methods and systems are provided for facilitating time zone prediction using electronic communication data. Electronic message data associated with a message recipient of electronic communications is obtained. The electronic message data includes message delivery data associated with an electronic message and message response data associated with a response, by the message recipient, to a received electronic message. Using a machine learning model and based on the message delivery data and the message response data, a time-zone score is determined for a time zone. Such a time-zone score can indicate a probability the time zone corresponds with the message recipient. Based on the time-zone score, the time zone is identified as corresponding with the message recipient.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.