Patents by Inventor Jun He

Jun He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250036797
    Abstract: Provided are a detection method and apparatus for privacy information leakage and an electronic device. The detection method for privacy information leakage includes: acquiring an application to be detected, and performing reverse parsing on the application to obtain a parsed target file; performing static analysis on the target file to obtain a dynamic loading path and a target privacy protocol of the application; generating a first detection result according to the target privacy protocol and a preset protocol; detecting, according to the dynamic loading path, user privacy information used by the application in a dynamic loading process to generate a second detection result; and determining, according to the first detection result and the second detection result, whether the application is an abnormal application causing leakage of the user privacy information.
    Type: Application
    Filed: April 21, 2022
    Publication date: January 30, 2025
    Inventors: Wenyue LI, Yisheng HE, Wangjunjie ZHANG, Jun XU, Zhenghan WANG
  • Patent number: 12210558
    Abstract: The present disclosure describes techniques of storing and accessing multimedia files. The techniques comprise obtaining at least two multimedia files; performing format parsing for each of the at least two multimedia files separately to obtain audio encoding data, video encoding data, and container format data of each of the at least two multimedia files; storing the container format data of each of the at least two multimedia files separately, and storing one copy of the audio encoding data and video encoding data; and generating and storing index data comprising information of identifying encoding offset of the container format data, the audio encoding data, and the video encoding data in each of the at least two multimedia files, and comprising information indicative of storage address of the container format data, the audio encoding data, and the video encoding data of each of the at least two multimedia files.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: January 28, 2025
    Assignee: SHANGHAI BILIBILI TECHNOLOGY CO., LTD.
    Inventors: Jun He, Yi Wang
  • Publication number: 20250019302
    Abstract: This invention discloses a rare earth energy-saving admixture and its preparation method for cement kilns, involving the field of energy saving and emission reduction technology for cement kilns. The invention, without changing or minimally changing existing hardware equipment, reduces the thermal consumption of the production system and sulfur-nitrogen and sulfur emissions by conducting a thermodynamic diagnosis and calculating the amount of rare earth energy-saving admixture to be added, thereby saving the cost of retrofitting large hardware equipment.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Applicants: BAOTOU HONGRUN RARE EARTH TECIINOLOGY CO.,LTD., BEIJING HONGKERUIDA ENGINEERING CO.,LTD.
    Inventors: Jinzheng HE, Jun ZHANG, Lixin LU, Quansen ZHANG
  • Publication number: 20250020941
    Abstract: An electronic device may include a stereoscopic display that is configured to display three-dimensional content for a viewer. The stereoscopic display may include a lenticular lens film with lenticular lenses that extend across the length of the display and may be referred to as a lenticular display. The lenticular display may have convex curvature. The lenticular display may include a color filter layer with color filters and an opaque masking layer. The color filter layer may be interposed between the lenticular lens film and an array of display pixels for the display. The color filter layer may mitigate ghost image artifacts and reflections of ambient light. Microlenses may be included between the lenticular lens film and the array of display pixels to improve the efficiency of the display. The display may include a Fresnel lens layer. The lenticular lens film may include lenticular lenses having different shapes.
    Type: Application
    Filed: June 7, 2024
    Publication date: January 16, 2025
    Inventors: Hao Chen, ByoungSuk Kim, Fu-Chung Huang, Juan He, Jun Qi, Ping-Yen Chou, Yi Huang, Yi-Pai Huang
  • Patent number: 12199352
    Abstract: Provided are tuning circuit and communication device. The tuning circuit includes tuning switch, ground patch point, and at least two sets of patch units. Each set of patch units at least includes a first patch point and a second patch point; the tuning switch comprises a standard port and at least one conversion port, and each set of patch units is connected to the corresponding conversion port; a first end of a first patch point and a first end of a second patch point in the same set of patch units are connected to the same conversion port; second ends of first patch points in different patch units are respectively connected to different contact points of an antenna; the second ends of all the second patch points are connected to the ground; and both ends of the ground patch point are respectively connected to the standard port and the ground.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: January 14, 2025
    Assignee: ANHUI ANUKI TECHNOLOGIES CO., LTD.
    Inventors: Lei Xu, Chengjie Zuo, Jun He
  • Publication number: 20250009769
    Abstract: The present disclosure provides use of lysophosphatidic acid (LPA) as a feed additive in controlling porcine infectious diarrhea, and belongs to the technical field of feed nutrition. The LPA is a type of lipid substance that is produced endogenously in vivo and can reduce a large secretion level of intestinal fluid in piglets caused by Escherichia coli infection via inhibiting cystic fibrosis transmembrane-conductance regulator (CFTR)-dependent iodine efflux. In this way, a susceptibility of weaned piglets to the Escherichia coli is prevented to effectively maintain the intestinal health of piglets. LPA is an endogenous substance in vivo, and it is first discovered that adding the LPA into a feed can control Escherichia coli-caused infectious diarrhea in the piglets.
    Type: Application
    Filed: March 7, 2024
    Publication date: January 9, 2025
    Inventors: Jie YU, Wenting DU, Daiwen CHEN, Hui YAN, Bing YU, Jun HE, Ping ZHENG, Xiangbing MAO, Aimin WU, Yueqi XUAN
  • Patent number: 12186952
    Abstract: An injection mould and an injection moulding method are provided. The injection mould includes: a base plate, configured to place a package chip to be injection-moulded, the package chip including a substrate and at least one chip fixed on a surface of the substrate by a flip chip process, the substrate having a through hole, a glue injection channel being formed in the base plate and configured to inject a moulding compound, and the glue injection channel being connected with the through hole on the substrate. The above-mentioned injection mould can improve the reliability of the package chip after injection moulding.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 7, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jun He, Jie Liu, Changhao Quan, Zhan Ying
  • Patent number: 12170327
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Te Chen, Hui-Ting Tsai, Jun He, Kuo-Feng Yu, Chun Hsiung Tsai
  • Publication number: 20240395666
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a metal line over a first substrate, a second substrate over the metal line, and a through-via penetrating through the second substrate and landing on the metal line. The through-via includes a copper fill having at least 85% (111) crystal orientation. The through-via includes a top portion with a first top width over a bottom portion with a second top width that is smaller than the first top width, and the top portion includes a first bulk portion over a first footing feature. The first bulk portion has first sidewalls, the first footing feature has second sidewalls, and the second sidewalls slant inwards from the first sidewalls to narrow the through-via from the first top width of the top portion to the second top width of the bottom portion.
    Type: Application
    Filed: September 26, 2023
    Publication date: November 28, 2024
    Inventors: Yao-Chun Chuang, Tsung-Yu Ke, Chang-Jung Hsueh, Min-Feng Ku, Jun He
  • Publication number: 20240394507
    Abstract: The disclosure relates to a method, apparatus, system, medium and electronic device for graph neural network generation. The method includes: obtaining a subgraph structure, the subgraph structure being configured to reflect a graph structure of a corresponding subgraph, and the subgraph comprising a plurality of nodes and edges between the plurality of nodes; obtaining, based on the subgraph structure and according to a predetermined priority, node features of the plurality of nodes and edge features of the edges from a plurality of memories; the predetermined priority being obtained by sorting the plurality of memories in accordance with memory size in an ascending order; fusing, based on the subgraph structure, the node features of the plurality of nodes and the edge features of the edges to obtain subgraph data; and training, based on the subgraph data, the graph neural network.
    Type: Application
    Filed: November 4, 2022
    Publication date: November 28, 2024
    Inventors: Yibo ZHU, Yangrui CHEN, Jun HE, Yanghua PENG, Chuanxiong GUO, Jian WANG
  • Publication number: 20240395750
    Abstract: One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.
    Type: Application
    Filed: September 13, 2023
    Publication date: November 28, 2024
    Inventors: Jui Shen CHANG, Yu-Chang LAI, Chen-Nan CHIU, Yao-Chun CHUANG, Jun HE
  • Publication number: 20240395621
    Abstract: A method includes receiving a first wafer having a first device layer on a first semiconductor substrate, receiving a second wafer having a second device layer on a second semiconductor substrate, forming a first groove along a first scribing channel of the first wafer with a non-mechanical cutting process, and forming a second groove along a second scribing channel of the second wafer with the non-mechanical cutting process. The method further includes after the forming of the first and second grooves, bonding the first and second wafers together, and dicing the bonded first and second wafers through the first and second grooves with a mechanical cutting process.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Patent number: 12144795
    Abstract: The present disclosure relates to the preparation of a highly pure cannabidiol compound by a novel synthesis route. The cannabidiol compound can be prepared by an acid-catalyzed reaction of a di-halo olivetol with menthadienol, followed by two crystallization steps. The highly pure cannabidiol compound is produced in high yield, stereospecificity, or both, and shows exceedingly low levels of ?-9-tetrahydrocannabinol at the time of preparation and after storage.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 19, 2024
    Assignee: PURISYS LLC
    Inventors: Daniel M. Hallow, Jun He, Mark C. Dobish, Denis Petrovic, Gnel Mkrtchyan
  • Publication number: 20240378216
    Abstract: Providing Quality of Service (QOS) for replicating datasets including: receiving, by a target data repository from a source data repository, a checkpoint describing one or more updates to one or more datasets stored in the source data repository and the target data repository; adding, by the target data repository, the checkpoint to a first queue for checkpoints directed to one or more volumes in the target data repository, wherein the first queue is included in a plurality of queues for the target data repository; selecting, by the target data repository, one or more queues from the plurality of queues; and servicing an operation from each of the selected one or more queues.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: DANIEL SONNER, JUN HE, ZONG WANG, JOHN COLGROVE, MATTHEW FAY
  • Publication number: 20240379825
    Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: MING-TE CHEN, HUI-TING TSAI, JUN HE, KUO-FENG YU, CHUN HSIUNG TSAI
  • Publication number: 20240371780
    Abstract: A semiconductor device with a multi-tier construction includes a first tier having a first die, a second die spaced apart from the first die in a first direction and a fill material therebetween. A second tier overlays the first tier, and includes a bridge die partially overlaying the fill material and the first and second dies. The bridge die provides an electrical interconnection between the first and second dies in the first tier. The device also has a first protective structure aligned with a first interface between an end of the first die and the fill material that includes a first part formed on a first side of the first die at the end of the first die; and a second part formed on a first side of the bridge die. The first and second parts are aligned and form the first protective structure, mitigating cracking near the bridge die.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Inventors: Li-Hsien Huang, Jun He, Yinlung Lu, Yao-Chun Chuang
  • Publication number: 20240361380
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
  • Patent number: 12131951
    Abstract: Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 29, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuxian Liao, Jie Liu, Jun He, Lixia Zhang, Zhan Ying
  • Patent number: 12132463
    Abstract: Provided are balun circuit structure and balun device, the balun circuit structure comprises unbalanced terminal, first and second balanced terminals, grounded power terminal, first, second, third and fourth inductors. The first terminal of the first inductor is connected to the first terminal of the second inductor, the second terminal of the first inductor is connected to the unbalanced terminal, the second terminal of the second inductor is open-circuited, the first terminal of the third inductor and the first terminal of the fourth inductor are connected to the grounded power terminal, the second terminal of the third inductor is connected to the first balanced terminal, the second terminal of the fourth inductor is connected to the second balanced terminal, the first, second, third and fourth inductors are located in different planes, respectively, the first inductor is coupled to the third inductor, and the second inductor is coupled to the fourth inductor.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: October 29, 2024
    Assignee: ANHUI ANUKI TECHNOLOGIES CO., LTD.
    Inventors: Wei Cheng, Chengjie Zuo, Jun He
  • Publication number: 20240352688
    Abstract: A stiffening girder erection method of a ground-anchored suspension bridge is provided. Clips for all hanger rods of a space main cable suspension bridge are installed such that design center lines of the clips are located in a vertical plane. A first stiffening girder section is installed at a position away from a first tower at a preset distance in a longitudinal direction. A second stiffening girder section is installed at a position away from a second tower at the preset distance along the longitudinal direction. A plurality of third stiffening girder sections are installed one by one in a direction respectively from the first stiffening girder and the second stiffening girder toward a mid-span until a mid-span closure is completed. An azimuth angle of a main cable around a central axis thereof at each of the clips is measured.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Chuanxi LI, Hu WANG, Hongjun KE, Jun HE, Jiping WANG