Abstract: A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.

Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.

Abstract: A semiconductor structure including a reliable power rail in stacked field effect transistor technology with unequal device footprints is provided that mitigates, and in some cases even eliminates, shorting risks that are typically associated using long bars in advanced logic applications.

Abstract: Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form an extended-gate field effect transistor (EG-FET) on a substrate. The fabrication operations include forming a channel in an EG region of the substrate. A first EG gate dielectric is deposited over the channel at a first low-temperature. A reinforcement treatment is applied to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric. The first low-temperature is selected to be below the second low-temperature; and the second low-temperature is selected to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level or rate.

Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a second transistor, vertically stacked on the first transistor, including a second source/drain region. The semiconductor device includes an isolation layer positioned between the first transistor and the second transistor and an air gap positioned between the first source/drain region and the isolation layer.

Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.

Abstract: A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A p-channel field-effect transistor (pFET) having a source/drain region is formed, where: a bottom surface of the source/drain region is of a depth lower than a bottom surface of a gate region; and the source/drain region comprises a silicon germanium alloy doped with boron; An n-channel field-effect transistor (nFET) is formed. A via is formed, where the via has a top surface above a top surface of the nFET. The semiconductor structure is flipped. A substrate is selectively removed respective to the source/drain region. A backside interlayer dielectric (ILD) is formed, where the backside ILD is of a different material than a shallow trench isolation layer. A backside contact is formed, where the backside contact contacts the source/drain region and the via.

Abstract: Aspects of the invention are directed to fabrication methods and resulting structures for providing transistors having hybrid crystal orientation channels and mixed crystal orientation bottom epitaxies. In a non-limiting embodiment, a first fin having a first crystal orientation is formed in a first region of a substrate having a second crystal orientation. A second fin having the second crystal orientation is formed in a second region of the substrate. The second fin is formed directly on a surface of the substrate. A mixed crystal bottom source or drain region is formed between the first fin and the first region of the substrate and a single crystal bottom source or drain region having the second crystal orientation is formed on sidewalls of the second fin and on the surface of the substrate in the second region.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: A microelectronic structure that includes a stacked FET that includes an upper FET and a lower FET, wherein the upper FET includes a NFET source/drain and the lower FET includes a PFET source/drain, wherein the PFET source/drain extends past a backside surface of a lower gate of the lower FET into a backside region of the stacked FET. A first backside interlayer dielectric layer located adjacent to a sidewall of the PFET source/drain that extends into the backside region. A second backside interlayer dielectric layer located on a backside surface of the first backside interlayer dielectric layer. A backside contact located on a backside surface of the PFET source/drain.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

Abstract: A device includes a base layer structure including a first region and a second region; a first bottom gate material in a plurality of first-type doped regions in the first and second regions; a second bottom gate material in a second-type doped regions in the first and second regions; first nanosheet gate-all-round device structures on the first bottom gate material; and second nanosheet gate-all-round device structures on the second bottom gate material, wherein the first bottom gate material is located over the second nanosheet gate-all-around device structures in the second-type doped regions of the first and second regions, wherein the second bottom gate material extends, in boundary regions between the first-type and second-type doped regions, on the base layer structure from the second nanosheet gate-all-around devices structures toward the first gate-all-round device structures.

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

Abstract: Bonded stacked FETs with individually tunable gate dielectrics are provided. In one aspect, a stacked FET device includes: a bottom transistor disposed on a wafer; and a top transistor bonded on top of the bottom transistor via a bonding layer, where the bottom transistor includes a stack of first active layers, a first gate dielectric disposed on the first active layers, and a first gate electrode disposed on the first gate dielectric, where the top transistor includes a stack of second active layers, a second gate dielectric disposed on the second active layers, and a second gate electrode disposed on the second gate dielectric, and where the first gate dielectric has at least one of a different composition and a different thickness from the second gate dielectric. A method of forming the present stacked FET devices is also provided.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: A semiconductor device includes first and second source/drain regions, where the first source/drain region is at least partially laterally offset from the second source/drain region. The semiconductor device includes a first interlayer via extending into at least a portion of the first source/drain region, where the first interlayer via is isolated from the first source/drain region by a first dielectric liner, and a second interlayer via connected to the second source/drain region and to the first interlayer via, where the second interlayer via extends into at least a portion of the second source/drain region. The semiconductor device also includes a frontside contact connected to the first source/drain region, where the frontside contact is adjacent to, and isolated from, the second interlayer via.