Abstract: A semiconductor IC structure includes an upper transistor and lower transistor each with respective source/drain (S/D) regions. The upper S/D region includes a S/D cut sidewall. A first frontside contact is in contact with the upper S/D region and includes a first conductive portion with a first cut sidewall that is substantially coplanar with the S/D cut sidewall. A second frontside contact is in contact with the lower S/D region and includes a second conductive portion with a second cut sidewall. A contact cut region may be between the first and second frontside contacts. This structure may be fabricated at least in part by forming a monolithic frontside contact against the lower S/D region and against the upper S/D region and simultaneously separating the monolithic frontside contact into the first frontside contact and the second frontside contact while removing a portion of the upper S/D region.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Abstract: Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.

Abstract: Semiconductor devices includes a bottom field effect transistor (FET) over a substrate, having a bottom channel and bottom source/drain structures. A bottom plug of dielectric material penetrates the substrate and that makes contact with a channel of the bottom FET. A top FET over the bottom FET has a top channel that is laterally offset with respect to the bottom channel. Electrical contacts reach to the top FET and the bottom FET.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

Abstract: A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.

Abstract: A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

Abstract: A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked nanosheet structure and a second stacked nanosheet structure each including a first nanosheet structure formed at a first level and a second nanosheet structure formed at a second level. A configuration of the first stacked nanosheet structure on the first level is different than a configuration of the second stacked nanosheet structure on the first level, or the configuration of the first stacked nanosheet structure on the second level is different than a configuration of the second stacked nanosheet structure on the second level.

Abstract: A semiconductor structure is provided that includes a lateral passive diode co-integrated with nanosheet stacked FET technology. Notably, the semiconductor structure includes a passive/diode device region including a lateral passive diode that is located between two nanosheet stacks. In embodiments, a logic device region including a stacked nanosheet transistor is located adjacent to the passive/diode device region.

Abstract: A semiconductor device is provided and includes a first transistor including a first source/drain (S/D) region, a second transistor stacked over the first transistor and including a second S/D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S/D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S/D region and the second BPR are connected by the metallization.

Abstract: A semiconductor structure is provided that includes a backside dielectric cap which seals the gate structure thus preventing gate structure exposure during backside processing. The presence of the backside dielectric cap helps to mitigate gate to direct backside source/drain contact shorts. The backside dielectric cap is formed during frontside processing.

Abstract: A semiconductor device includes a stacked transistor structure including a column having field effect transistors on two levels in the column, the two levels including a top tier and bottom tier. First channels of a field effect transistor are disposed on a first side of the column at the top tier and second channels of a second field effect transistor disposed on a second side of the column opposite the first side at the bottom tier to form an offset between the first channels and the second channels within the column.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers and a first interfacial layer surrounding each of the plurality of first nanosheet channel layers, the first interfacial layer having a first thickness, and a second nanosheet field-effect transistor device vertically stacked above the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers and a second interfacial layer surrounding each of the plurality of second nanosheet channel layers, the second interfacial layer having a second thickness greater than the first thickness. A distance between each of the plurality of second nanosheet channel layers is less than a distance between each of the plurality of first nanosheet channel layers.

Abstract: A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.

Abstract: Embodiments of the disclosure are directed to an integrated circuit (IC) that includes a bottom device and a top device positioned over the bottom device. The top device includes a first nanosheet and a second nanosheet. The bottom device includes a third nanosheet and a fourth nanosheet. A space between the first nanosheet and the second nanosheet is greater than a space between the third nanosheet and the fourth nanosheet.

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Abstract: A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.