Abstract: A black body radiation device is provided, which can be used as a benchmark heat source for “thermal imager” temperature detection device. The black body radiation device includes: a heat source module comprising a heater and a temperature equalizing plate, wherein the temperature equalizing plate contacts the heater; a temperature control module connected to the heater to control the heater, thereby keeping the temperature equalizing plate at a predetermined temperature; and a housing configured to accommodate the heat source module and the temperature control module, the housing having an opening, wherein the opening is configured to expose the temperature equalizing plate.

Abstract: A light-emitting device includes: a substrate having a top surface, wherein the top surface comprises a first portion and a second portion; a first semiconductor stack on the first portion, comprising a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, comprising a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack comprises a dislocation stop layer; wherein the dislocation stop layer comprises AlGaN; and wherein the first side wall and the second portion of the top surface form an acute angle a between thereof

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

Abstract: The present application provides an optical network method and associated apparatus. The method includes: receiving uplink burst time assignment information; and enabling or disabling a laser module of a local end according to the uplink burst time assignment information.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank and may not contact the blending tank. The slurry blending tool may include a blending pump partially provided within the blending tank and to blend the one or more materials into the slurry. The slurry blending tool may include an outlet pipe connected to the blending pump and to remove the slurry from the blending tank.

Abstract: A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Abstract: A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.

Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

Abstract: A chemical dispensing system is capable of simultaneously supplying a semiconductor processing chemical for production and testing through the use of independent chemical supply lines, which reduces production downtime of an associated semiconductor process, increases throughput and capability of the semiconductor process, and/or the like. Moreover, the capability to simultaneously supply the semiconductor processing chemical for production and testing allows for an increased quantity of semiconductor processing chemical batches to be tested with minimal impact to production, which increases quality control over the semiconductor processing chemical. In addition, the independent chemical supply lines may be used to supply the semiconductor processing chemical to production while independently filtering semiconductor processing chemical directly from a storage drum through a filtration loop.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first component in a substrate. The semiconductor arrangement includes a gap fill layer. A first portion of the gap fill layer overlies the first component. The first portion of the gap fill layer has a tapered sidewall. A first portion of the substrate separates the first portion of the gap fill layer from the first component.

Abstract: A notebook computer includes an upper part, a lower part, a delay linkage module, and a hinge portion connected to the lower part and the upper part. The delay linkage module includes a delay linking rod, a linkage member, a guide rod and a connecting shaft. The linkage member is fixedly connected to the hinge portion, and pivotally connected to the delay linking rod. The guide rod is pivotally connected to a second display screen and a fixing base of the lower part. The connecting shaft is connected to the guide rod, and slidably located in an elongated through hole of the delay linking rod. when a first display screen of the upper part is rotated away from the lower part, the hinge portion pulls the delay linkage module to rotate the second display screen being lifted up from the lower part.

Abstract: A notebook computer includes an upper part, a lower part, a delay linkage module, and a hinge portion connected to the lower part and the upper part. The delay linkage module includes a delay linking rod, a linkage member, a guide rod and a connecting shaft. The linkage member is fixedly connected to the hinge portion, and pivotally connected to the delay linking rod. The guide rod is pivotally connected to a second display screen and a fixing base of the lower part. The connecting shaft is connected to the guide rod, and slidably located in an elongated through hole of the delay linking rod. when a first display screen of the upper part is rotated away from the lower part, the hinge portion pulls the delay linkage module to rotate the second display screen being lifted up from the lower part.

Abstract: A light-emitting device includes a substrate having a top surface, wherein the top surface includes a first portion and a second portion; a first semiconductor stack on the first portion, including a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, including a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack includes a dislocation stop layer; and wherein the first side wall and the second portion of the top surface form an acute angle ? between thereof.

Abstract: An optical sensing method and an optical sensor module thereof. The optical sensing method includes obtaining an optical signal by sensing with a first optical sensor and a second optical sensor, respectively. The first optical sensor and the second optical sensor have different optical sensing wavelength ranges. Furthermore, a color temperature determination unit receives the optical signals of the first and second optical sensors and calculates a color temperature value by substituting an equation. In this way, the optical sensing method and its optical sensor module can obtain color temperature calculations with high accuracy and can effectively reduce the system computational complexity.

Abstract: A method of stabilizing performance of a processing device may include determining a maximum operational temperature of any number of cores of a processing device from a thermal control circuit of the processing device; setting a maximum power based on a maximum thermal capacity of the processing device to a power lower than the maximum operational temperature; increasing the power provided to the processing device when the maximum thermal capacity is below a set temperature; and placing the power provided to the processing device to an intermediate power level relative to the operational temperature and the maximum thermal capacity when operations of the processing device are to exceed the operational temperature of any of the cores of the processing device.

Abstract: A method of selectively removing aluminium oxide or nitride material from a microelectronic substrate, the method comprising contacting the material with an aqueous etching composition comprising: an etchant comprising a source of fluoride; and a metal corrosion inhibitor; wherein the composition has a pH in the range of from 3 to 8. Aqueous etching compositions and uses are also described.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.